Huff / Gilmer High Dielectric Constant Materials

VLSI MOSFET Applications
1. Auflage 2005
ISBN: 978-3-540-26462-0
Verlag: Springer Berlin Heidelberg
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, Band 16, 710 Seiten

Reihe: Springer Series in Advanced Microelectronics

Issues relating to the high-K gate dielectric are among the greatest challenges for the evolving International Technology Roadmap for Semiconductors (ITRS). More than just an historical overview, this book will assess previous and present approaches related to scaling the gate dielectric and their impact, along with the creative directions and forthcoming challenges that will define the future of gate dielectric scaling technology.

Autoren/Hrsg.

Huff, H.R.

Gilmer, D.C.

Huff, Howard

Gilmer, David

Inhaltsverzeichnis

1;Preface;6
2;Contents;9
3;List of Contributors;20
4;1 The Economic Implications of Moore’s Law;24
4.1;1.1 Introduction;24
4.2;1.2 Moore’s Law: A Description;24
4.3;1.3 The History of Moore’s Law;25
4.4;1.4 The Microeconomics of Moore’s Law;36
4.5;1.5 The Macroeconomics of Moore’s Law;44
4.6;1.6 Moore’s Law Meets Moore’s Wall: What is Likely to Happen;46
4.7;1.7 Conclusion;50
4.8;1.8 Appendix A;51
4.9;References;53
5;Classical Regime for SiO2;54
5.1;2 Brief Notes on the History of Gate Dielectrics in MOS Devices;55
5.1.1;2.1 Early Attempts to Make Insulating- Gate Field- Effect Transistors; Surface States;55
5.1.2;2.2 Passivation of Silicon Surfaces by Thermal Oxidation; Planar Transistor Technology;56
5.1.3;2.3 Positive Oxide Charge and Surface States at the Si– SiO2 Interface;57
5.1.4;2.4 Instabilities Due to Ion Drift Effects;58
5.1.5;2.5 Phosphate-silicate Glass Helped;59
5.1.6;2.6 Other Materials Tried as Gate-Dielectric Layers;59
5.1.7;2.7 Thermal Oxidation of Silicon;60
5.1.8;2.8 Segregation of Dopants at the Si– SiO2 Interface;61
5.1.9;2.9 Other Silicon Oxide Preparation Techniques;62
5.1.10;2.10 Thick Field Oxides;63
5.1.11;2.11 Breakdown Strength of SiO2, Defect Density, Moore’s Law;63
5.1.12;2.12 Weak Oxide Regions in MOS Structures, Kooi Effect;63
5.1.13;2.13 Al Gate MOS Devices; PMOS IC’s;64
5.1.14;2.14 Silicon Gate MOS Devices, NMOS and CMOS IC’s;64
5.1.15;2.15 Decrease of Oxide Thickness Connected with Downscaling of MOS Structure;65
5.1.16;References;65
5.2;3 SiO2 Based MOSFETS: Film Growth and Si– SiO2 Interface Properties;67
5.2.1;3.1 SiO2 Prior to 1970;67
5.2.2;3.2 After 1970: Progress in Understanding;77
5.2.3;3.3 Modern Era: The Quest for Thinner SiO2 and Alternatives;98
5.2.4;References;108
5.3;4 Oxide Reliability Issues;113
5.3.1;4.1 Thin Oxide Layer Degradation Under Electrical Stress;113
5.3.2;4.2 Oxide Breakdown;124
5.3.3;4.3 Breakdown Acceleration Models;129
5.3.4;4.4 Conclusion;133
5.3.5;References;133
6;Transition to Silicon Oxynitrides;143
6.1;5 Gate Dielectric Scaling to 2.0–1.0 nm: SiO2 and Silicon Oxynitride;144
6.1.1;5.1 Device Requirements on Gate Dielectric Scaling;144
6.1.2;5.2 Definition of Gate Dielectric Thickness;148
6.1.3;5.3 Tunneling Current of SiO2;153
6.1.4;5.4 Tunneling Currents of Silicon Oxynitride;156
6.1.5;5.5 Application Dependence of Gate Dielectric Limit;158
6.1.6;References;161
6.2;6 Optimal Scaling Methodologies and Transistor Performance;164
6.2.1;6.1 Introduction;164
6.2.2;6.2 Scaling and Device Physics;166
6.2.3;6.3 Limitations of Conventional Scaling;175
6.2.4;6.4 Extending Validity of Moore’s Law;186
6.2.5;6.5 Conclusions;211
6.2.6;References;213
6.3;7 Silicon Oxynitride Gate Dielectric for Reducing Gate Leakage and Boron Penetration Prior to High- k Gate Dielectric Implementation;216
6.3.1;7.1 Introduction;216
6.3.2;7.2 Integrated RTCVD Oxynitride (ION) Process;218
6.3.3;7.3 JVD Nitride;228
6.3.4;7.4 DPN Oxynitride;232
6.3.5;7.5 Conclusion;239
6.3.6;References;240
7;Transition to High-k Gate Dielectrics;242
7.1;8 Alternative Dielectrics for Silicon- Based Transistors: Selection Via Multiple Criteria;243
7.1.1;8.1 Introduction;243
7.1.2;8.2 Discussion;246
7.1.3;8.3 Conclusions;267
7.1.4;References;268
7.2;9 Materials Issues for High- k Gate Dielectric Selection and Integration;272
7.2.1;9.1 Introduction;272
7.2.2;9.2 MIS (Metal-Insulator-Semiconductor) Structures;276
7.2.3;9.3 Materials Properties and Integration Considerations;280
7.2.4;9.4 Conclusions;296
7.2.5;References;296
7.3;10 Designing Interface Composition and Structure in High Dielectric Constant Gate Stacks;306
7.3.1;10.1 Introduction;306
7.3.2;10.2 Thermodynamic Stability of Dielectrics on Silicon;309
7.3.3;10.3 Kinetic Rate Processes During Metal Oxide Deposition;316
7.3.4;10.4 Gate Electrode/Dielectric Interfaces;323
7.3.5;10.5 Conclusion;324
7.3.6;References;325
7.4;11 Electronic Structure of Alternative High- k Dielectrics;330
7.4.1;11.1 Introduction;330
7.4.2;11.2 SiO2 and the Si–SiO2 Interface;332
7.4.3;11.3 Alternative Dielectrics;341
7.4.4;11.4 Electronic Structure of Transition Metal Dielectrics;346
7.4.5;11.5 Experimental Studies of Electronic Structure;352
7.4.6;11.6 Interface Electronic Structure Applied to Direct Tunneling in Silicate Alloys;367
7.4.7;11.7 Conclusion;372
7.4.8;References;374
7.5;12 Physicochemical Properties of Selected 4d, 5d, and Rare Earth Metals in Silicon;377
7.5.1;12.1 Introduction;377
7.5.2;12.2 Crystal Lattice Site of 4d, 5d, and Rare Earth Metals in Silicon;378
7.5.3;12.3 Solubility of 4d, 5d, and Rare Earth Metals in Silicon;379
7.5.4;12.4 Diffusivity of 4d, 5d, and Rare Earth Elements in Silicon;380
7.5.5;12.5 Energy Levels in the Band Gap;386
7.5.6;12.6 Effect of 4d, 5d, and Rare Earth Metals on Minority Carrier Recombination Lifetime and Device Performance;390
7.5.7;12.7 Summarizing Discussion;392
7.5.8;References;393
7.6;13 High-k Gate Dielectric Deposition Technologies;397
7.6.1;13.1 Atomic Layer Deposition;398
7.6.2;13.2 Chemical Vapor Deposition;409
7.6.3;13.3 Plasma-Enhanced Atomic Layer Deposition;411
7.6.4;13.4 Plasma Enhanced Chemical Vapor Deposition;414
7.6.5;13.5 Physical Vapor Deposition;417
7.6.6;13.6 Molecular Beam Epitaxy;421
7.6.7;13.7 Ion Beam Assisted Deposition;422
7.6.8;13.8 Sol-gel Deposition;423
7.6.9;13.9 Summary;424
7.6.10;References;425
7.7;14 Issues in Metal Gate Electrode Selection for Bulk CMOS Devices;432
7.7.1;14.1 Background;432
7.7.2;14.2 Metal Gate Selection Criteria;433
7.7.3;14.3 Other Challenges with Metal Gates;435
7.7.4;14.4 Metal Gate Candidates for NMOS Devices;436
7.7.5;14.5 Metal Candidates for PMOS Devices;447
7.7.6;14.6 Metals on High-k Dielectrics;447
7.7.7;14.7 Conclusion;448
7.7.8;References;449
7.8;15 CMOS IC Fabrication Issues for High- k Gate Dielectric and Alternate Electrode Materials;452
7.8.1;15.1 Introduction;452
7.8.2;15.2 The "Standard” CMOS Flow;453
7.8.3;15.3 Insertion of High-k Gate Dielectric into the CMOS Flow;459
7.8.4;15.4 Alternative Electrode Materials;466
7.8.5;15.5 Integration of High-k Gate Dielectrics and Metal Gates into Advanced Devices;478
7.8.6;15.6 Conclusions;487
7.8.7;References;488
7.9;16 Characterization and Metrology of Medium Dielectric Constant Gate Dielectric Films;499
7.9.1;16.1 Introduction;499
7.9.2;16.2 Structural and Chemical Characterization of Medium e Film Stacks;502
7.9.3;16.3 Optical Models for Medium k Films;519
7.9.4;References;533
7.10;17 Electrical Measurement Issues for Alternative Gate Stack Systems;537
7.10.1;17.1 Introduction;537
7.10.2;17.2 Capacitance–Voltage Measurement;538
7.10.3;17.3 Analysis of Device/Material Parameters from Established C– V Data;564
7.10.4;17.4 Current-Voltage Measurement;567
7.10.5;17.5 Determination of DC Conduction Mechanisms;572
7.10.6;17.6 Sample Design and Preparation Issues;576
7.10.7;17.7 Conclusion;578
7.10.8;References;578
7.11;18 High-k Gate Dielectric Materials Integrated Circuit Device Design Issues;583
7.11.1;18.1 Introduction;583
7.11.2;18.2 Fundamental Issues on Gate Capacitance and Current Modeling;584
7.11.3;18.3 Wave Function Penetration Effect Issues;595
7.11.4;18.4 Maxwell–Wagner Effects and Power Law Dispersion;607
7.11.5;18.5 Conclusions;618
7.11.6;References;619
8;Future Directions for Ultimate Scaling Technology Generations;621
8.1;19 High-k Crystalline Gate Dielectrics: A Research Perspective;622
8.1.1;19.1 Introduction;622
8.1.2;19.2 The Path to the Perovskites and COS;625
8.1.3;19.3 The Material System of COS;629
8.1.4;19.4 The Implementation of COS;634
8.1.5;19.5 Electrical Properties;644
8.1.6;19.6 Conclusion;649
8.1.7;References;650
8.2;20 High-k Crystalline Gate Dielectrics: An IC Manufacturer’s Perspective;653
8.2.1;20.1 Introduction;653
8.2.2;20.2 Theoretical Overview;658
8.2.3;20.3 Perovskite Surface;658
8.2.4;20.4 Oxide Deposition;661
8.2.5;20.5 Growth Template;662
8.2.6;20.6 Substrate Preparation;663
8.2.7;20.7 Initial Nucleation;664
8.2.8;20.8 Stability of the Interface;667
8.2.9;20.9 Structural Properties;668
8.2.10;20.10 Band Discontinuity;672
8.2.11;20.11 Device Results;675
8.2.12;20.12 Conclusion;677
8.2.13;References;678
8.3;21 Advanced MOS-Devices;681
8.3.1;21.1 Introduction;681
8.3.2;21.2 The Ballistic Nanotransistor;688
8.3.3;21.3 Vertical Replacement Gate MOSFET;695
8.3.4;21.4 The Double-Gate FinFET;702
8.3.5;21.5 Silicon-On-Nothing MOSFETs;706
8.3.6;21.6 Conclusion;715
8.3.7;References;716
9;Index;720