Heath Microprocessor Architectures

RISC, CISC and DSP
2. Auflage 2014
ISBN: 978-1-4832-9553-4
Verlag: Elsevier Science & Techn.
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 400 Seiten, Web PDF

'Why are there all these different processor architectures and what do they all mean? Which processor will I use? How should I choose it?' Given the task of selecting an architecture or design approach, both engineers and managers require a knowledge of the whole system and an explanation of the design tradeoffs and their effects. This is information that rarely appears in data sheets or user manuals. This book fills that knowledge gap.Section 1 provides a primer and history of the three basic microprocessor architectures. Section 2 describes the ways in which the architectures react with the system. Section 3 looks at some more commercial aspects such as semiconductor technology, the design cycle, and selection criteria. The appendices provide benchmarking data and binary compatibility standards. Since the first edition of this book was published, much has happened within the industry. The Power PC architecture has appeared and RISC has become a more significant challenger to CISC. The book now includes new material on Power PC, and a complete chapter devoted to understanding the RISC challenge. The examples used in the text have been based on Motorola microprocessor families, but the system considerations are also applicable to other processors. For this reason comparisons to other designs have been included, and an overview of other processors including the Intel 80x86 and Pentium, DEC Alpha, SUN Sparc, and MIPS range has been given. Steve Heath has been involved in the design and development of microprocessor based systems since 1982. These designs have included VMEbus systems, microcontrollers, IBM PCs, Apple Macintoshes, and both CISC and RISC based multiprocessor systems, while using operating systems as varied as MS-DOS, UNIX, Macintosh OS and real time kernels. An avid user of computer systems, he has written numerous articles and papers for the electronics press, as well as books from Butterworth-Heinemann including VMEbus: A Practical Companion; PowerPC: A Practical Companion; MAC User's Pocket Book; UNIX Pocket Book; Upgrading Your PC Pocket Book; Upgrading Your MAC Pocket Book; and Effective PC Networking.

Senior Staff Engineer, European Strategy and Technology Development, Motorola Semiconductors, Steve Heath has written 15 books on topics covering Apple and IBM PCs, processor architectures, UNIX and Windows NT operating systems.

Autoren/Hrsg.

Heath, Steve

Inhaltsverzeichnis

1;Front Cover;1
2;Microprocessor Architectures RISC, CISC and DSP;4
3;Copyright Page;5
4;Table of Contents;6
5;Preface;14
6;Acknowledgements;16
7;Chapter 1. Complex instruction set computers;18
7.1;8 bit microprocessors: the precursors of CISC;18
7.2;8 bit microprocessor register models;20
7.3;Requirements for a new processor architecture;26
7.4;Software compatibility;27
7.5;Enter the MC68000;29
7.6;Complex instructions, microcode and nanocode;30
7.7;The MC68000 hardware;32
7.8;Typical system;41
7.9;Multitasking operating systems;49
7.10;Context switching, task tables and kernels;51
7.11;Start of a revolution;55
7.12;The MC68010 virtual memory processor;56
7.13;Virtual memory support;56
7.14;Virtual machine support;59
7.15;MC68010 SUPERVISOR resource;60
7.16;Other improvements;61
7.17;The MC68008;62
7.18;The story continues;63
8;Chapter 2. 32 bit CISC processors;64
8.1;Enter HCMOS technology;64
8.2;Architectural challenges;65
8.3;The MC68020 32 bit performance standard;67
8.4;The internal design philosophy;68
8.5;The programmer's model;70
8.6;Dynamic bus sizing;74
8.7;On chip instruction cache;76
8.8;Debugging support;80
8.9;Coprocessor interface;82
8.10;MC68881 and MC68882 floating point coprocessors;84
8.11;The MC68651 paged memory management unit (PMMU);87
8.12;The MC68030: the first commercial 50 MHz processor;88
8.13;Memory management;91
9;Chapter 3. The RISC challenge;94
9.1;The 80/20 rule;94
9.2;The initial RISC research;95
9.3;The Berkeley model;96
9.4;The Stanford model;97
9.5;The catalysts;97
9.6;The M88000 family;98
9.7;M88000 concurrent functional units;100
9.8;Multiple execution units and optimisation;101
9.9;Scoreboarding;103
9.10;Delayed branching;105
9.11;The MC88100 programming model;106
9.12;Handling exceptions;107
9.13;The MC88100 instruction set;108
9.14;Addressing data;109
9.15;Fetching data;109
9.16;MC88100 external functions;111
9.17;Single-cycle memory buses;113
9.18;MC88200 cache MMU;114
9.19;Memory management functions;115
9.20;Cache coherency;116
9.21;The MBUS protocol;117
9.22;M88000 master / checker fault tolerance;119
9.23;Future enhancements;119
10;Chapter 4. RISC wars;121
10.1;RISC versus CISC;121
10.2;Enter the MC68040;122
10.3;Superscalar alternatives;131
10.4;Superpipelining;132
10.5;Very long instruction word;133
10.6;Superscalar principles;134
10.7;Controlling multiple instructions per clock;136
10.8;Software control;138
10.9;The MC88110;139
10.10;Enter the PowerPC;143
10.11;The PowerPC architectural model;144
10.12;Execution pipelines;147
10.13;Branch delays;153
10.14;Branch folding;155
10.15;Static branch prediction;157
10.16;Branch prediction cache;158
10.17;Register renaming;159
10.18;The MPC601 block diagram;161
10.19;The MPC603 block diagram;163
11;Chapter 5. Digital signal processors;165
11.1;Processor requirements;169
11.2;The DSP56000 family;170
11.3;Basic architecture;170
11.4;The programming model;178
11.5;The instruction set;180
11.6;Arithmetic and logical instructions;180
11.7;Bit manipulation;182
11.8;Loop control;182
11.9;MOVE commands;183
11.10;Program control;183
11.11;Instruction format;184
11.12;Using special addressing and loop modes;184
11.13;Internal parallelism;185
11.14;Architectural differences;186
11.15;DSP96000 — combining integration and performance;186
11.16;OnCE — a new approach to emulation;188
12;Chapter 6. Memory, memory management and caches;189
12.1;Achieving processor throughput;189
12.2;Partitioning the system;191
12.3;Shadow RAM;192
12.4;DRAM versus SRAM;193
12.5;Optimising the DRAM interface;194
12.6;Page mode operation;194
12.7;Page interleaving;195
12.8;Alternative memory systems;197
12.9;Burst mode SRAM;197
12.10;Big vs. little endian organization;199
12.11;Memory management;201
12.12;Disadvantages of memory management;203
12.13;Segmentation and paging;204
12.14;Multitasking and user / supervisor conflicts;209
12.15;Table walking and RISC architectures;211
12.16;Instruction continuation versus restart;216
12.17;Memory management and DSP;216
12.18;Cache memory;217
12.19;Cache size and organization;217
12.20;Optimising line length and cache size;222
12.21;Logical versus physical caches;223
12.22;Unified versus Harvard caches;224
12.23;Cache coherency;225
12.24;Case 1: write through;226
12.25;Case 2: write back;227
12.26;Case 3: no caching of write cycles;228
12.27;Case 4: write buffer;228
12.28;Bus snooping;228
12.29;The MESI protocol;234
12.30;The MEI protocol;235
12.31;Streaming and CWF (critical word first);236
12.32;Cache control instructions;238
12.33;Implementing memory systems;239
12.34;Secondary or level 2 caches;239
12.35;Conclusions;240
13;Chapter 7. Real-time software, interrupts and exceptions;241
13.1;What is real-time software;241
13.2;Responding to an interrupt;242
13.3;Improving performance;245
13.4;Interrupting CISC and RISC processors;245
13.5;RISC interrupt service routines;246
13.6;Improving software performance;248
13.7;Addressing data;248
13.8;Fetching data;248
13.9;Testing data;250
13.10;Saving and restoring register sets;251
13.11;Interrupting the DSP56000;252
13.12;Diadic versus triadic instruction sets;253
13.13;Instruction restart versus instruction continuation;254
13.14;External memory and real-time performance;254
13.15;Register windowing;256
13.16;Combining architectures;256
13.17;The M68300 family;258
13.18;Software considerations;260
13.19;Combining DSP processors;261
13.20;Conclusions;264
14;Chapter 8. Multiprocessing;265
14.1;SISD — single instruction, single data;265
14.2;SIMD — single instruction, multiple data;266
14.3;MIMD — multiple instruction, multiple data;267
14.4;MISD — multiple instruction, single data;268
14.5;Constructing a MIMD architecture;268
14.6;Processor bandwidths;270
14.7;Profiling;271
14.8;Cost of memory access;272
14.9;Fault tolerant systems;275
14.10;Single- and multiple-threaded operating systems;278
15;Chapter 9. Application examples;281
15.1;MC68020 and MC68030 design techniques for high reliability applications;281
15.2;Upgrading 8 bit systems;291
15.3;Transparent update techniques for digital filters using the DSP56000;296
15.4;Motor and servo control;299
15.5;Improved SRAM interfaces;305
16;Chapter 10. Semiconductor technology;312
16.1;Silicon technology;312
16.2;CMOS and bipolar technology;314
16.3;Fabrication technology;316
16.4;Packaging;317
16.5;Processor technology;320
16.6;Memory technology;320
16.7;Science fiction or not;322
17;Chapter 11. The changing design cycle;323
17.1;The shortening design cycle;323
17.2;The double-edged sword of technology;325
17.3;Make versus buy;325
17.4;Simulation versus emulation;331
18;Chapter 12. The next generations;344
18.1;MC68000 — superscalar CISC;344
18.2;The MPC604;345
18.3;The future for CISC;346
18.4;An alternative direction — system integration;347
18.5;The M68300 family;347
18.6;Improving the instruction set;351
18.7;Summary;353
19;Chapter 13. Selecting a micro-processor architecture;355
19.1;Meeting performance needs;355
19.2;Choice of platforms;355
19.3;Anticipating future needs;356
19.4;Software support;356
19.5;Development support;357
19.6;Standards;360
19.7;Built-in obsolescence;361
19.8;Market changes;361
19.9;Considering all the options;362
20;Appendices;363
20.1;A 'Lies, damn lies and benchmarks';363
20.2;B Alternative micro-processor architectures;369
21;Index;400