Heath Microprocessor Architectures and Systems

RISC, CISC and DSP
1. Auflage 2014
ISBN: 978-1-4832-7824-7
Verlag: Elsevier Science & Techn.
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 302 Seiten, Web PDF

Microprocessor Architectures and Systems: RISC, CISC, and DSP focuses on the developments of Motorola's CISC, RISC, and DSP processors and the advancements of the design, functions, and architecture of microprocessors. The publication first ponders on complex instruction set computers and 32-bit CISC processors. Discussions focus on MC68881 and MC68882 floating point coprocessors, debugging support, MC68020 32-bit performance standard, bus interfaces, MC68010 SUPERVISOR resource, and high-level language support. The manuscript then covers the RISC challenge, digital signal processing, and memory management and caches. Topics include implementing memory systems, multitasking and user/supervisor conflicts, partitioning the system, cache size and organization, DSP56000 family, MC88100 programming model, M88000 family, and the 80/20 rule. The text examines the selection of a microprocessor architecture, changing design cycle, semiconductor technology, multiprocessing, and real-time software, interrupts, and exceptions. Concerns include locating associated tasks, MC88100 interrupt service routines, single- and multiple-threaded operating systems, and the MC68300 family. The publication is a valuable reference for computer engineers and researchers interested in microprocessor architectures and systems.

Senior Staff Engineer, European Strategy and Technology Development, Motorola Semiconductors, Steve Heath has written 15 books on topics covering Apple and IBM PCs, processor architectures, UNIX and Windows NT operating systems.

Autoren/Hrsg.

Heath, Steve

Inhaltsverzeichnis

1;Front Cover;1
2;Microprocessor Architectures and Systems: RISC, CISC and DSP;4
3;Copyright Page;5
4;Dedication;6
5;Table of Contents;8
6;Preface;12
7;Acknowledgements;14
8;Chapter 1. Complex instruction setcomputers;16
8.1;8-bit microprocessors: the precursors of CISC;16
8.2;8-bit microprocessor register models;18
8.3;Restrictions;19
8.4;Addressing memory;21
8.5;System integrity;22
8.6;Requirements for a new processor architecture;23
8.7;Software compatibility;24
8.8;Enter the MC68000;26
8.9;Complex instructions, microcode and nanocode;27
8.10;The MC68000 hardware;29
8.11;M68000 asynchronous bus;31
8.12;M6800 synchronous bus;34
8.13;Interrupts;34
8.14;Error recovery and control signals;35
8.15;Bus arbitration;37
8.16;Typical system;38
8.17;The register set;38
8.18;The USER/SUPERVISOR concept;40
8.19;Exceptions and the vector table;41
8.20;Addressing modes;43
8.21;Instruction set;44
8.22;High-level language support;49
8.23;Start of a revolution;51
8.24;The MC68010 virtual memory processor;51
8.25;MC68010 SUPERVISOR resource;55
8.26;Other improvements;56
8.27;The MC68008;57
8.28;The story continues;58
9;Chapter 2. 32-bit CISC processors;59
9.1;Enter HCMOS technology;59
9.2;Architectural challenges;60
9.3;The MC68020 32-bit performance standard;62
9.4;The programmer's model;64
9.5;Bus interfaces;67
9.6;Dynamic bus sizing;68
9.7;On-chip instruction cache;70
9.8;Debugging support;74
9.9;Coprocessor interface;75
9.10;MC68881 and MC68882 floating point coprocessors;78
9.11;The MC68851 paged memory management unit (PMMU);79
9.12;The MC68030 - the first commercial 50 MHz processor;81
10;Chapter 3. The RISC challenge;87
10.1;The 80/20 rule;87
10.2;The initial RISC research;88
10.3;The M88000 family;91
10.4;The MC88100 programming model;98
10.5;The MC88100 instruction set;100
10.6;MC88100 external functions;103
10.7;MC88200 cache MMU;106
10.8;The MBUS protocol;109
11;Chapter 4. Digital signal processing;113
11.1;Processor requirements;116
11.2;The DSP56000 family;117
11.3;The programming model;125
12;Chapter 5. Memory, memory managementand caches;134
12.1;Achieving processor throughput;134
12.2;Partitioning the system;136
12.3;Shadow RAM;137
12.4;DRAM v. SRAM;138
12.5;Memory management;142
12.6;Multitasking and user/supervisor conflicts;149
12.7;Cache size and organization;152
12.8;Cache coherency;158
12.9;Implementing memory systems;166
12.10;Conclusions;167
13;Chapter 6. Real-time software, interrupts and exceptions;169
13.1;What is real-time software?;169
13.2;Responding to an interrupt;170
13.3;Interrupting the processor;170
13.4;Servicing the interrupt;170
13.5;Locating associated tasks;171
13.6;Context switches;172
13.7;Improving performance;173
13.8;Interrupting an MC88100;173
13.9;MC88100 interrupt service routines;174
13.10;Interrupting the DSP56000;178
13.11;The M68300 family;184
13.12;Conclusions;189
14;Chapter 7. Multiprocessing;190
14.1;SISD - Single instruction, single data;191
14.2;SIMD - Single instruction, multiple data;191
14.3;MIMD - Multiple instruction, multiple data;192
14.4;MISD - Multiple instruction, single data;192
14.5;Constructing a MIMD architecture;193
14.6;Fault-tolerant systems;199
14.7;Single- and multiple-threaded operating systems;202
15;Chapter 8. Application ideas;204
15.1;1 MC68020 and MC68030 design techniques for highreliability applications;204
15.2;2 Upgrading 8-bit systems;213
15.3;3 Transparent update techniques for digital filters usingthe DSP56000;217
15.4;4 Motor and servo control;220
16;Chapter 9. Semiconductor technology;228
16.1;Silicon technology;228
16.2;CMOS and bipolar technology;230
16.3;Fabrication technology;232
16.4;Packaging;233
16.5;Processor technology;236
16.6;Memory technology;236
16.7;Science fiction or not?;237
17;Chapter 10. The changing design cycle;239
17.1;The shortening design cycle;239
17.2;The double-edged sword of technology;241
17.3;Make v. Buy;241
17.4;Simulation v. emulation;247
18;Chapter 11. The next generations;252
18.1;Enter the MC68040;252
18.2;The MC68300 family;261
18.3;Improving the instruction set;265
18.4;DSP96000 - combining integration and performance;271
19;Chapter 12. Selecting a microprocessor architecture;274
19.1;Meeting performance needs;274
19.2;Software support;275
19.3;Development support;276
19.4;Standards;278
19.5;Built-in obsolescence;280
19.6;Market changes;280
19.7;Considering all the options;281
20;Appendix A: Benchmarking;282
21;Appendix B: Binary compatibilitystandards;288
22;Index;295