Harris | Skew-Tolerant Circuit Design | Buch | 978-1-55860-636-4 | sack.de

Buch, Englisch, 300 Seiten, Format (B × H): 188 mm x 234 mm, Gewicht: 494 g

Reihe: The Morgan Kaufmann Computer A

Harris

Skew-Tolerant Circuit Design


Neuausgabe 2000
ISBN: 978-1-55860-636-4
Verlag: MORGAN KAUFMANN PUBL INC

Buch, Englisch, 300 Seiten, Format (B × H): 188 mm x 234 mm, Gewicht: 494 g

Reihe: The Morgan Kaufmann Computer A

ISBN: 978-1-55860-636-4
Verlag: MORGAN KAUFMANN PUBL INC


As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers.This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues.

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Zielgruppe


Engineers designing high-speed microprocessors and DSPs as well as postgraduate students in advanced VLSI design courses


Autoren/Hrsg.


Weitere Infos & Material


Chapter 1 - Introduction Chapter 2 - Fundamental Concepts Chapter 3 - IP Switching Chapter 4 - Tag Switching Chapter 5 - MPLS Core Protocols Chapter 6 - Quality of Service Chapter 7 - Constraint­based routing Chapter 8 - Virtual Private Networks


Harris, David
David Harris is the Harvey S. Mudd Professor of Engineering Design at Harvey Mudd College. He received his Ph.D. in electrical engineering from Stanford University and his M.Eng. in electrical engineering and computer science from MIT. Before attending Stanford, he worked at Intel as a logic and circuit designer on the Itanium and Pentium II processors. Since then, he has consulted at Sun Microsystems, Hewlett-Packard, Broadcom, and other design companies. David holds more than a dozen patents and is the author of three other textbooks on chip design, as well as many Southern California hiking guidebooks. When he is not working, he enjoys hiking, flying, and making things with his three sons.



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