Power-Aware Testing and Test Strategies for Low Power Devices

2010. Auflage 2009
ISBN: 978-1-4419-0927-5
Verlag: Springer Us

Buch, Englisch, 363 Seiten, Format (B × H): 164 mm x 244 mm, Gewicht: 1590 g

Managing the power consumption of circuits and systems is now considered one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as dynamic voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and EDA solutions for testing low power devices.

Zielgruppe

Research

Autoren/Hrsg.

Girard, Patrick

Nicolici, Nicola

Wen, Xiaoqing

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Technische Wissenschaften Technik Allgemein Konstruktionslehre und -technik
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Halb- und Supraleitertechnologie

Inhaltsverzeichnis

Fundamentals of VLSI Testing.- Power Issues During Test.- Low-Power Test Pattern Generation.- Power-Aware Design-for-Test.- Power-Aware Test Data Compression and BIST.- Power-Aware System-Level Test Planning.- Low-Power Design Techniques and Test Implications.- Test Strategies for Multivoltage Designs.- Test Strategies for Gated Clock Designs.- Test of Power Management Structures.- EDA Solution for Power-Aware Design-for-Test.