Franklin / Crowley / Hadimioglu Network Processor Design

Issues and Practices
1. Auflage 2002
ISBN: 978-0-08-051249-5
Verlag: Elsevier Science & Techn.
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 338 Seiten, Web PDF

Reihe: The Morgan Kaufmann Series in Computer Architecture and Design

As the demand for digital communication networks has increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility, and economy requirements, the networking industry has opted to build products around network processors. These new chips range from task-specific processors, such as classification and encryption engines, to more general-purpose packet or communications processors. Programmable yet application-specific, their designs are tailored to efficiently implement communications applications such as routing, protocol analysis, voice and data convergence, firewalls, VPNs, and QoS. Network processor design is an emerging field with issues and opportunities both numerous and formidable. To help meet this challenge, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers from academia and industry to discuss their latest research in the architecture, design, programming, and use of these devices. In addition to including the results of the Workshop in this volume, the editors also present specially commissioned material from practicing designers, who discuss their companies' latest network processors. Network Processor Design: Issues and Practices is an essential reference on network processors for graduate students, researchers, and practicing designers.* Includes contributions from major academic and industrial research labs including Aachen University of Technology; Cisco Systems; Infineon Technologies; Intel Corp.; North Carolina State University; Swiss Federal Institute of Technology; University of California, Berkeley; University of Dortmund; University of Washington; and Washington University. * Examines the latest network processors from Agere Systems, Cisco, IBM, Intel, Motorola, Sierra Inc., and TranSwitch.

Mark A. Franklin received his B.A., B.S.E.E. and M.S.E.E. from Columbia University, and his Ph.D. in EE from Carnegie-Mellon University. He is currently at Washington University in St. Louis where he has a joint appointment in Electrical Engineering and Computer Science, and holds the Urbauer Chair in Engineering. He founded and is Director of the Computer and Communications Research Center and until recently was the Director of the Undergraduate Program in Computer Engineering. Dr. Franklin is engaged in research, teaching and consulting in the areas of computer and communications architectures, ASIC and embedded processor design, parallel and distributed systems, and systems performance evaluation. He is a Fellow of the IEEE, a member of the ACM, and has been an organizer and reviewer for numerous professional conferences including the HPCA8 Workshop on Network Processors (2002). He has been Chair of the IEEE TCCA (Technical Committee on Computer Architecture), and Vice-Chairman of the ACM SIGARCH (Special Interest Group on Computer Architecture).

Autoren/Hrsg.

Franklin, Mark A.

Crowley, Patrick

Hadimioglu, Haldun

Onufryk, Peter Z.

Inhaltsverzeichnis

1;Front Cover;1
2;Network Processor Design Issues and Practices;2
3;Copyright Page;5
4;Contents;6
5;Preface;14
6;Chapter 1. Network Processors: An Introduction to Design Issues;16
6.1;1.1 Design Challenges;18
6.2;1.2 Design Techniques;19
6.3;1.3 Challenges and Conclusions;22
7;PART I: DESIGN PRINCIPLES;24
7.1;Chapter 2. Benchmarking Network Processors;26
7.1.1;2.1 Benchmarking Framework Overview;27
7.1.2;2.2 Hardware-Level Benchmarks;30
7.1.3;2.3 Microlevel Benchmarks;33
7.1.4;2.4 Function-Level Benchmarks;36
7.1.5;2.5 Related Work;38
7.1.6;References;39
7.2;Chapter 3. A Methodology and Simulator for the Study of Network Processors;42
7.2.1;3.1 Previous Work;43
7.2.2;3.2 Component Network Simulator (ComNetSim);45
7.2.3;3.3 The Cisco Toaster2;47
7.2.4;3.4 Implementation of ComNetSim;50
7.2.5;3.5 Application Development;59
7.2.6;3.6 Organization and Configuration;63
7.2.7;3.7 Experiments and Results;63
7.2.8;3.8 Conclusion and Future Work;67
7.2.9;References;68
7.3;Chapter 4. Design Space Exploration of Network Processor Architectures;70
7.3.1;4.1 Models for Streams, Tasks, and Resources;73
7.3.2;4.2 Analysis Using a Scheduling Network;78
7.3.3;4.3 Multiobjective Design Space Exploration;94
7.3.4;4.4 Case Study;96
7.3.5;Acknowledgments;101
7.3.6;References;102
7.4;Chapter 5. Compiler Backend Optimizations for Network Processors with Bit Packet Addressing;106
7.4.1;5.1 Bit-Level Data Flow Analysis and Bit Value Inference;110
7.4.2;5.2 Code Selection;114
7.4.3;5.3 Register Allocation Considering Register Arrays;121
7.4.4;5.4 Dead Code Elimination;124
7.4.5;5.5 Implementation;125
7.4.6;5.6 Results;127
7.4.7;Acknowledgments;128
7.4.8;References;128
7.5;Chapter 6. A Network Processor Performance and Design Model with Benchmark Parameterization;132
7.5.1;6.1 The Performance Model;134
7.5.2;6.2 Workload and System Characteristics;141
7.5.3;6.3 Design Results;145
7.5.4;6.4 Conclusion;153
7.5.5;References;153
7.6;Chapter 7. A Benchmarking Methodology for Network Processors;156
7.6.1;7.1 Related Work;158
7.6.2;7.2 A Benchmarking Methodology;161
7.6.3;7.3 The Benchmark Suite;173
7.6.4;7.4 Preliminary Results;175
7.6.5;7.5 Conclusion and Future Work;178
7.6.6;References;179
7.7;Chapter 8. A Modeling Framework for Network Processor Systems;182
7.7.1;8.1 Framework Description;183
7.7.2;8.2 System Modeling;192
7.7.3;8.3 IPSec VPN Decryption;199
7.7.4;8 .4 Packet Size Distributions;201
7.7.5;8.5 Conclusion and Future Work;202
7.7.6;Acknowledgments;202
7.7.7;References;202
8;PART II: PRACTICES;204
8.1;Chapter 9. An Industry Analyst's Perspective on Networ k Processors;206
8.1.1;9.1 History of Packet Processing;206
8.1.2;9.2 The Need for Programmability;214
8.1.3;9.3 Network Processors;218
8.1.4;9.4 Where Do NPs Fit in a System?;220
8.1.5;9.5 Evaluating NP Solutions;224
8.1.6;9.6 Trends;230
8.2;Chapter 10. Agere Systems—Communications Optimized PayloadPlus Network Processor Architecture;234
8.2.1;10.1 Target Applications;235
8.2.2;10.2 PayloadPlus Optimized Pipeline-Based Hardware Architecture;235
8.2.3;10.3 3G/Media Gateway Application Example;240
8.2.4;10.4 FPP Details;240
8.2.5;10.5 RSP details;243
8.2.6;10.6 Software Architecture and Overview;245
8.2.7;10.7 Agere Performance Benefits at OC-48c;247
8.2.8;References;248
8.3;Chapter 11. Cisco Systems— Toaster 2;250
8.3.1;11.1 Target Application(s);250
8.3.2;11.2 Packet Flow Example for a Centralized System;253
8.3.3;11.3 Packet Flow Example for a Distributed System;254
8.3.4;11.4 Toaster2 Hardware Architecture;255
8.3.5;11.5 External Memory Controller;256
8.3.6;11.6 Internal Column Memory;256
8.3.7;11.7 Input and Output Header Buffers;256
8.3.8;11.8 Toaster MicroController;257
8.3.9;11.9 Tag Buffer;260
8.3.10;11.10 Route Processor interface;260
8.3.11;11.11 Lock Controller;260
8.3.12;11.12 Software Architecture;261
8.3.13;11.13 Toaster Development Methodology and Environment;261
8.3.14;11.14 Performance Claims;262
8.3.15;11.15 Family of Toaster Network Processors;263
8.3.16;11.16 Conclusion;263
8.4;Chapter 12. IBM—PowerNP Network Processor;264
8.4.1;12.1 Hardware Architecture;266
8.4.2;12.2 Software;270
8.4.3;12.3 Performance;272
8.4.4;12.4 Conclusion;273
8.4.5;Acknowledgments;273
8.4.6;References;273
8.5;Chapter 13. Intel Corporation—Intel IXP2400 Network Processor: A Second-Generation Intel NPU;274
8.5.1;13.1 Target Applications;274
8.5.2;13.2 Hardware Architecture;275
8.5.3;13.3 Software Development Environment;281
8.5.4;13.4 IXP2400 System Configurations and Performance Analysis;288
8.5.5;13.5 CONCLUSION;289
8.5.6;References;290
8.6;Chapter 14. Motorola—C-5e Network Processor;292
8.6.1;14.1 Target Applications;293
8.6.2;14.2 Hardware Architecture;295
8.6.3;14.3 Software Architecture;302
8.6.4;14.4 Conclusion;305
8.6.5;References;305
8.7;Chapter 15. PMC-Sierra, Inc.— ClassiPI;306
8.7.1;15.1 Target Applications;306
8.7.2;15.2 ClassiPl Architecture;309
8.7.3;15.3 System Interface (SI);310
8.7.4;15.4 Field Extraction Engine (FEE);310
8.7.5;15.5 Classification Engine (CE);310
8.7.6;15.6 External RAM (ERAM) Interface;312
8.7.7;15.7 ClassiPI Control and Sequencer Block;312
8.7.8;15.8 Cascade Interface;313
8.7.9;15.9 ClassiPI Implementation;314
8.7.10;15.10 Software Architecture and Development Kit;314
8.7.11;15.11 Platforms;314
8.7.12;15.12 Modules;315
8.7.13;15.13 Software Development;315
8.7.14;15.14 Simulator;316
8.7.15;15.15 Debugger;316
8.7.16;15.16 ClassiPl Application Example : A Complex Security-Enabled Router;317
8.7.17;15.17 Performance;319
8.7.18;15.18 Conclusion;319
8.7.19;References;320
8.8;Chapter 16. TranSwitch—ASPEN: Flexible Network Processing for Access Solutions;322
8.8.1;16.1 Applications;322
8.8.2;16.2 ASPEN Operation and Architecture;325
8.8.3;16.3 Programming Environment;331
8.8.4;16.4 Conclusion;332
8.8.5;References;333
9;Index;334
10;About the Editors;352