E-Book, Englisch, 318 Seiten
Foster / Krolnik Creating Assertion-Based IP
2008
ISBN: 978-0-387-68398-0
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark
E-Book, Englisch, 318 Seiten
Reihe: Integrated Circuits and Systems
ISBN: 978-0-387-68398-0
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark
This book presents formal testplanning guidelines with examples focused on creating assertion-based verification IP. It demonstrates a systematic process for formal specification and formal testplanning, and also demonstrates effective use of assertions languages beyond the traditional language construct discussions Note that there many books published on assertion languages (such as SystemVerilog assertions and PSL). Yet, none of them discuss the important process of testplanning and using these languages to create verification IP. This is the first book published on this subject.
Autoren/Hrsg.
Weitere Infos & Material
1;TABLE OF CONTENTS;7
2;FOREWORD;12
3;PREFACE;14
3.1;Open Verification Methodology;16
3.2;Acknowledgements;16
4;INTRODUCTION;18
4.1;1.1 Assertion- Based IP;18
4.2;1.2 Properties and assertions;26
4.3;1.3 Who should read this book?;31
4.4;1.4 Book organization;32
4.5;1.5 Summary;34
5;DEFINITIONS AND TERMINOLOGY;35
5.1;2.1 Notation;36
5.2;2.2 Verification component description;41
5.3;2.3 Verification component organization;42
5.4;2.4 Definitions;47
5.5;2.5 Acronyms;51
5.6;2.6 Summary;52
6;THE PROCESS;53
6.1;3.1 Guiding principles;54
6.2;3.2 Process steps;55
6.3;3.3 Assertion- based IP architecture;57
6.4;3.4 Guidelines and conventions;73
6.5;3.5 Summary;73
7;BUS-BASED DESIGN EXAMPLE;74
7.1;4.1 Bus- based design overview;75
7.2;4.2 Summary;76
8;INTERFACES;77
8.1;5.1 Simple generic serial bus interface;78
8.2;5.2 Simple generic nonpipelined bus interface;89
8.3;5.3 Simple generic pipelined bus interface;103
8.4;5.4 Interface monitor coverage example;122
8.5;5.5 Summary;126
9;ARBITERS;127
9.1;6.1 Arbitrations schemes;128
9.2;6.2 Creating an arbiter assertion- based IP;148
9.3;6.3 Summary;156
10;CONTROLLERS;158
10.1;7.1 Simple generic memory controller;159
10.2;7.2 Summary;187
11;DATAPATH;189
11.1;8.1 Multiport register file;191
11.2;8.2 Data queue;210
11.3;8.3 Data error correction;226
11.4;8.4 Data compression;237
11.5;8.5 Data decompression;251
11.6;8.6 Summary;263
12;QUICK TUTORIAL FOR SVA;265
12.1;A. 1 SVA fundamentals;265
12.2;A. 2 SystemVerilog sequences;270
12.3;A. 3 Property declarations;275
12.4;A. 4 Sequence and property operators;276
12.5;A. 5 SVA system functions and task;280
12.6;A. 6 Dynamic data within sequences;284
12.7;A. 7 SVA directives;285
12.8;A. 8 Useful named property examples;286
13;COMPLETE OVM/AVM TESTBENCH EXAMPLE;287
13.1;B. 1 OVM/ AVM Example Source Code;288
13.2;B. 2 OVM/ AVM high- level reference guide;313
14;BIBLIOGRAPHY;316
15;Index;319
