Buch, Englisch, 141 Seiten, Paperback, Format (B × H): 187 mm x 235 mm, Gewicht: 259 g
Buch, Englisch, 141 Seiten, Paperback, Format (B × H): 187 mm x 235 mm, Gewicht: 259 g
Reihe: Synthesis Lectures on Computer Architecture
ISBN: 978-1-59829-584-9
Verlag: Morgan & Claypool Publishers
With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip network design and provide the reader with an overview of the current state-of-the-art research in this field.
Autoren/Hrsg.
Weitere Infos & Material
- Introduction
- Interface with System Architecture
- Topology
- Routing
- Flow Control
- Router Microarchitecture
- Conclusions
