Deng / Maly 3-Dimensional VLSI

A 2.5-Dimensional Integration Scheme
1. Auflage 2010
ISBN: 978-3-642-04157-0
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 200 Seiten

'3-Dimensional VLSI: A 2.5-Dimensional Integration Scheme'elaborates the concept and importance of 3-Dimensional (3-D) VLSI. The authors have developed a new 3-D IC integration paradigm, so-called 2.5-D integration, to address many problems that are hard to resolve using traditional non-monolithic integration schemes. The book also introduces major 3-D VLSI design issues that need to be solved by IC designers and Electronic Design Automation (EDA) developers. By treating 3-D integration in an integrated framework, the book provides important insights for semiconductor process engineers, IC designers, and those working in EDA R&D. Dr. Yangdong Deng is an associate professor at the Institute of Microelectronics, Tsinghua University, China. Dr. Wojciech P. Maly is the U. A. and Helen Whitaker Professor at the Department of Electrical and Computer Engineering, Carnegie Mellon University, USA.

Autoren/Hrsg.

Deng, Yangdong

Maly, Wojciech P.

Inhaltsverzeichnis

1;Title page;2
2;Copyright Page;3
3;Preface;6
4;Acknowledgements;8
5;Table of Contents;9
6;List of Figures and Tables;13
7;1 Introduction;17
7.1;1.1 2.5-D Integration;21
7.2;1.2 Enabling Technologies;24
7.2.1;1.2.1 Fabrication Technology;24
7.2.2;1.2.2 Testing Methodology and Fault Tolerance Technique;25
7.2.3;1.2.3 Design Technology;26
7.3;1.3 Objectives and Book Organization;29
7.4;References;32
8;2 A Cost Comparison of VLSI Integration Schemes;37
8.1;2.1 Non-Monolithic Integration Schemes;38
8.1.1;2.1.1 Multiple-Reticle Wafer;39
8.1.2;2.1.2 Multiple Chip Module (MCM);39
8.1.3;2.1.3 Three-Dimensional (3-D) integration;40
8.2;2.2 Yield Analysis of Different VLSI Integration Approaches;42
8.2.1;2.2.1 Monolithic Soc;44
8.2.2;2.2.2 Multiple-Reticle Wafer (MRW);44
8.2.3;2.2.3 Three-Dimensional (3-D) Integration;46
8.2.4;2.2.4 2.5-D System Integration;47
8.2.5;2.2.5 Multi-Chip Module;50
8.2.6;2.2.6 Summing Up;51
8.3;2.3 Observations;53
8.4;References;54
9;3 Design Case Studies;58
9.1;3.1 Crossbar;59
9.2;3.2 A 2.5-D Rambus DRAM Architecture;62
9.2.1;3.2.1 Tackle the Long Bus Wire;62
9.2.2;3.2.2 Serialized Channel in the 3rd Dimension;64
9.3;3.3 A 2.5-D Redesign of PipeRench;66
9.3.1;3.3.1 The 2.5-D Implementation;68
9.3.2;3.3.2 Simulation Results;70
9.4;3.4 A 2.5-D Integrated Microprocessor System;72
9.4.1;3.4.1 A 2.5-D Integrated Microprocessor System;73
9.4.2;3.4.2 An Analytical Performance Model;78
9.4.3;3.4.3 Detailed Performance Simulation for Reduced Memory Latency;82
9.5;3.5 Observations;85
9.6;References;87
10;4 An Automatic 2.5-D Layout Design Flow;90
10.1;4.1 A 2.5-D Layout Design Framework;91
10.1.1;4.1.1 2.5-D Floorplanning;93
10.1.2;4.1.2 2.5-D Placement;94
10.1.3;4.1.3 2.5-D Global Routing;94
10.2;4.2 Observations;97
10.3;References;97
11;5 Floorplanning for 2.5-D Integration;99
11.1;5.1 Floorplan Level Evaluation—Category 2 Circuits;103
11.1.1;5.1.1 Technique;103
11.1.2;5.1.2 Results;105
11.2;5.2 Floorplan Level Evaluation—Category 3 Circuits;107
11.2.1;5.2.1 Technique;107
11.2.2;5.2.2 Results;108
11.3;5.3 Thermal driven floorplanning;109
11.3.1;5.3.1 Chip Level Thermal Modeling and Analysis for 2.5-D Floorplanning;111
11.3.2;5.3.2 Coupled Temperature and Leakage Estimation;115
11.3.3;5.3.3 2.5-D Thermal Driven Floorplanning Techniques;121
11.3.4;5.3.4 Experimental results;123
11.4;5.4 Observations;127
11.5;References;129
12;6 Placement for 2.5-D Integration;133
12.1;6.1 Pure Standard Cell Designs;135
12.1.1;6.1.1 Placement Techniques;136
12.1.2;6.1.2 Benchmarks and Layout Model;139
12.1.3;6.1.3 Evaluation of Vertical Partitioning Strategies;141
12.1.4;6.1.4 Wire length scaling;142
12.1.5;6.1.5 Wire length reduction;145
12.1.6;6.1.6 Wire Length vs. Inter-Chip Contact Pitch;149
12.2;6.2 Mixed Macro and Standard Cell Designs;150
12.2.1;6.2.1 Placement Techniques;152
12.2.2;6.2.2 Results and Analysis;154
12.3;6.3 Observations;156
12.4;References;158
13;7 A Road map of 2.5-D Integration;160
13.1;7.1 Stacked Memory;161
13.2;7.2 DRAM Integration for Bandwidth-Demanding Applications;163
13.3;7.3 Hybrid System Integration;167
13.4;7.4 Extremely High Performance Systems;171
13.4.1;7.4.1 Highly Integrated Image Sensor System;171
13.4.2;7.4.2 Radar-in-Cube;174
13.5;References;176
14;8 Conclusion and Future Work;180
14.1;8.1 Main Contributions and Conclusions;181
14.2;8.2 Future Work;184
14.2.1;8.2.1 Fabrication Technology for 2.5-D Systems;185
14.2.2;8.2.2 Testing Techniques for 2.5-D Integration;187
14.2.3;8.2.3 Design Technology for 2.5-D Integration;189
14.2.3.1;8.2.3.1 2.5-D Architecture Exploration tools;190
14.2.3.2;8.2.3.2 System Level Design Tools;194
14.2.3.3;8.2.3.3 Physical Design Tool Suite for 2.5-D ASICs;195
14.2.3.4;8.2.3.4 2.5-D VLSI Design Flow;199
14.3;References;202
15;Index;204