A Roadmap for Formal Property Verification

Softcover Nachdruck of hardcover 1. Auflage 2006
ISBN: 978-90-481-7185-9
Verlag: Springer Netherlands

Buch, Englisch, 252 Seiten, Previously published in hardcover, Format (B × H): 160 mm x 240 mm, Gewicht: 434 g

Integrating formal property verification (FPV) into an existing design process raises several interesting questions. This book develops the answers to these questions and fits them into a roadmap for formal property verification – a roadmap that shows how to glue FPV technology into the traditional validation flow. The book explores the key issues in this powerful technology through simple examples that mostly require no background on formal methods.

Zielgruppe

Research

Autoren/Hrsg.

Dasgupta, Pallab

Fachgebiete

• Mathematik | Informatik EDV | Informatik Professionelle Anwendung Computer-Aided Design (CAD)
• Technische Wissenschaften Technik Allgemein Technik: Allgemeines
• Technische Wissenschaften Technik Allgemein Computeranwendungen in der Technik
• Mathematik | Informatik EDV | Informatik Angewandte Informatik Computeranwendungen in Wissenschaft & Technologie
• Technische Wissenschaften Technik Allgemein Konstruktionslehre und -technik
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Geisteswissenschaften Design Produktdesign, Industriedesign
• Mathematik | Informatik EDV | Informatik Informatik Logik, formale Sprachen, Automaten
• Mathematik | Informatik EDV | Informatik Technische Informatik Hochleistungsrechnen, Supercomputer
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren

Inhaltsverzeichnis

Languages for Temporal Properties.- How Does the Property Checker Work?.- Is My Specification Consistent?.- Have I Written Enough Properties?.- Design Intent Coverage.- Test Generation Games.- A Roadmap for Formal Property Verification.

Über Autor(innen)

The author leads the Formal Verification Group at the Indian Institute of Technology, Kharagpur (http://www.facweb.iitkgp.ernet.in/~pallab/forverif.html). He has collaborations with leading companies, including Intel, Sun Microsystems, Synopsys, Texas Instruments, National Semiconductors, General Motors, Interra Systems and Virtio Corp, on developing formal methods for design verification. The author is a senior member of IEEE.