Buch, Englisch, 450 Seiten, Format (B × H): 152 mm x 229 mm, Gewicht: 771 g
Buch, Englisch, 450 Seiten, Format (B × H): 152 mm x 229 mm, Gewicht: 771 g
ISBN: 978-981-4364-02-7
Verlag: Pan Stanford
This book covers one of the most important device architectures that have been widely researched to extend the transistor scaling: FinFET. Starting with theory, the book discusses the advantages and the integration challenges of this device architecture. It addresses in detail the topics such as high-density fin patterning, gate stack design, and source/drain engineering, which have been considered challenges for the integration of FinFETs. The book also addresses circuit-related aspects, including the impact of variability on SRAM design, ESD design, and high-T operation. It discusses a new device concept: the junctionless nanowire FET.
Zielgruppe
Academic and Postgraduate
Autoren/Hrsg.
Fachgebiete
Weitere Infos & Material
General Introduction. Part 1: Integration of Multigate Devices (FinFET). Introduction to Multigate Devices and Integration Challenges. Patterning Requirements for Multigate Devices. Gate Stack Design. Source/Drain Design: Reduction of Parasitic Resistance.
Part 2: Circuit-Related Aspects. Variability and Its Implications for FinFET SRAM.
High T Performance of FinFET. ESD and Multigate Devices. Part 3: Beyond FinFET.
The Junctionless Nanowire Transistor. Transport in Nanostructures. Transport Spectroscopy of a Single Dopant in a Gated Silicon Nanowire. Thermionic Theory as a Tool for the Study of Transport in Doped and Undoped Si n-FINFETs Scaled Up to the Full Body Inversion Limit.