Chen / Lin / Hsiung | Hardware Software Co-Design of a Multimedia SOC Platform | E-Book | sack.de
E-Book

E-Book, Englisch, 152 Seiten, eBook

Chen / Lin / Hsiung Hardware Software Co-Design of a Multimedia SOC Platform


2009
ISBN: 978-1-4020-9623-5
Verlag: Springer Netherland
Format: PDF
 Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 152 Seiten, eBook

ISBN: 978-1-4020-9623-5
Verlag: Springer Netherland
Format: PDF
 Kopierschutz: 1 - PDF Watermark

is one of the first of its kinds to provide a comprehensive overview of the design and implementation of the hardware and software of an SoC platform for multimedia applications. Topics covered in this book range from system level design methodology, multimedia algorithm implementation, a sub-word parallel, single-instruction-multiple data (SIMD) processor design, and its virtual platform implementation, to the development of an SIMD parallel compiler as well as a real-time operating system (RTOS). is written for practitioner engineers and technical managers who want to gain first hand knowledge about the hardware-software design process of an SoC platform. It offers both tutorial-like details to help readers become familiar with a diverse range of subjects, and in-depth analysis for advanced readers to pursue further.

Chen / Lin / Hsiung Hardware Software Co-Design of a Multimedia SOC Platform jetzt bestellen!

Zielgruppe

Professional/practitioner

Autoren/Hrsg.

Chen, Sao-Jie
Lin, Guang-Huei
Hsiung, Pao-Ann
Hu, Yu-Hen

Weitere Infos & Material

Foreword by Giovanni de Micheli. Preface. Acknowledgments. List of Figures. List of Tables. 1. INTRODUCTION. 2. DESIGN CONSIDERATION. 1. Platform-Based Design. 2. System Modeling. 3. Video Coding. 4. Image Processing. 5. Cryptography. 6. Digital Communication. 7. Multimedia Instruction Set Design. 3. SYSTEM LEVEL DESIGN. 1. Abstraction Levels. 2. Algorithm Level Verification. 3. Transaction Level Modeling. 4. System Level Development Tools. 4. EMBEDDED PROCESSOR DESIGN. 1. Specific Instruction-Set. 2. Data Level Parallelism. 3. Instruction Level Parallelism. 4. Thread Level Parallelism. 5. PARALLEL COMPILER. 1. Vectorization. 2. Simdization. 3. ILP Scheduling. 4. Threading. 5. Compiler Technique. 6. Compiler Infrastructures. 6. IMPLEMENTATION OF H.264 ON PLX. 1. Instruction Set Decision for H.264. 2. Hardware/Software Partitioning. 3. Untimed Virtual Prototype. 4. Timed SystemC Modeling. 5. PLX Chip Design. 7. REAL-TIME OPERATING SYSTEM FOR PLX. 1. PRRP Scheduler. 2. Memory Management. 3. Communication and Synchronization Primitives. 4. Multimedia Applications in RTOS for PLX. 5. Application Development Environment. 6. Experimental Results. 8. CONCLUSION. References.

Ihre Fragen, Wünsche oder Anmerkungen
Vorname*
Nachname*
Ihre E-Mail-Adresse*
Kundennr.
Ihre Nachricht*
Lediglich mit * gekennzeichnete Felder sind Pflichtfelder.
Wenn Sie die im Kontaktformular eingegebenen Daten durch Klick auf den nachfolgenden Button übersenden, erklären Sie sich damit einverstanden, dass wir Ihr Angaben für die Beantwortung Ihrer Anfrage verwenden. Selbstverständlich werden Ihre Daten vertraulich behandelt und nicht an Dritte weitergegeben. Sie können der Verwendung Ihrer Daten jederzeit widersprechen. Das Datenhandling bei Sack Fachmedien erklären wir Ihnen in unserer Datenschutzerklärung.