Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Softcover Nachdruck of the original 1. Auflage 2014
ISBN: 978-3-319-34534-5
Verlag: Springer International Publishing

Buch, Englisch, 245 Seiten, Previously published in hardcover, Format (B × H): 155 mm x 235 mm, Gewicht: 4524 g

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

Zielgruppe

Professional/practitioner

Autoren/Hrsg.

Chakrabarty, Krishnendu

Noia, Brandon

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise

Inhaltsverzeichnis

Introduction.- Wafer Stacking and 3D Memory Test.- Built-in Self-Test for TSVs.- Pre-Bond TSV Test Through TSV Probing.- Pre-Bond TSV Test Through TSV Probing.- Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths.- Post-Bond Test Wrappers and Emerging Test Standards.- Test-Architecture Optimization and Test Scheduling.- Conclusions.

Über Autor(innen)

Krishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM.