Bosio / Dilillo / Girard Advanced Test Methods for SRAMs

Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies
1. Auflage 2009
ISBN: 978-1-4419-0938-1
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 171 Seiten

Modern electronics depend on nanoscaled technologies that present new challenges in terms of testing and diagnostics. Memories are particularly prone to defects since they exploit the technology limits to get the highest density. This book is an invaluable guide to the testing and diagnostics of the latest generation of SRAM, one of the most widely applied types of memory. Classical methods for testing memory are designed to handle the so-called 'static faults,' but these test solutions are not sufficient for faults that are emerging in the latest Very Deep Sub-Micron (VDSM) technologies. These new fault models, referred to as 'dynamic faults', are not covered by classical test solutions and require the dedicated test sequences presented in this book.

Autoren/Hrsg.

Bosio, Alberto

Dilillo, Luigi

Girard, Patrick

Pravossoudovitch, Serge

Virazel, Arnaud

Inhaltsverzeichnis

1;Acknowledgements;4
2;Advanced Test Solutions for Dynamic Faults in SRAM Memories;5
2.1;Authors of the book:;5
2.2;Summary and objective of the book:;5
3;Contents;6
4;General Introduction;9
4.1;History;9
4.2;SRAMs;10
4.3;Test of SRAMs;10
4.4;Organization of the Book;10
4.5;Description of Each Chapter;11
5;1 Basics on SRAM Testing;12
5.1;1.1 Overview of Semiconductor Memories;12
5.2;1.2 Typical Structure of an SRAM;14
5.3;1.3 The Context of SRAM Testing;16
5.3.1;1.3.1 Memory Model;17
5.3.2;1.3.2 Fault Model Representation;18
5.3.3;1.3.3 Fault Model Classification;19
5.3.4;1.3.4 Test Solutions and Algorithms;23
5.4;1.4 Test Generation;26
5.5;1.5 Test Validation;28
5.6;1.6 Conclusion;30
6;2 Resistive-Open Defects in Core-Cells;31
6.1;2.1 The SRAM Core-Cell;31
6.1.1;2.1.1 Reading in the Core-Cell;31
6.1.2;2.1.2 Writing in the Core-Cell;32
6.2;2.2 Analysis of Resistive-Open Defects in the Core-Cell;33
6.2.1;2.2.1 Defect Location;33
6.2.2;2.2.2 Defect Incidence Analysis;33
6.2.3;2.2.3 Simulation Set-Up and Results;36
6.3;2.3 Analysis and Test of dRDF;37
6.3.1;2.3.1 Functional Fault Modeling of dRDF;38
6.3.2;2.3.2 RES: Read Equivalent Stress;39
6.3.3;2.3.3 March Test Solutions Detecting dRDFs;43
6.4;2.4 Analysis and Test of dDRF;47
6.4.1;2.4.1 Functional Fault Modeling of dDRF;47
6.4.2;2.4.2 Experiments;48
6.4.2.1;2.4.2.1 dDRF Due to Defect Df4;50
6.4.2.2;2.4.2.2 dDRF Due to Defects Df2 and Df3;52
6.4.3;2.4.3 March Test Solution Detecting dDRFs;53
6.5;2.5 Impact of Technology Scaling;55
6.6;2.6 Conclusion;58
7;3 Resistive-Open Defects in Pre-charge Circuits;59
7.1;3.1 The SRAM Pre-charge Circuit;59
7.2;3.2 Analysis of Resistive-Open Defects in the Pre-charge Circuit;61
7.2.1;3.2.1 Defect Location;61
7.2.2;3.2.2 Defect Incidence Analysis;62
7.2.3;3.2.3 Simulation Set-Up and Results;63
7.3;3.3 Analysis and Test of URRF and URWF;64
7.3.1;3.3.1 Functional Fault Modeling of URRF and URWF;64
7.3.2;3.3.2 Experiments;65
7.3.3;3.3.3 March Test Solutions Detecting URWFs;70
7.4;3.4 Conclusion;74
8;4 Resistive-Open Defects in Address Decoders;75
8.1;4.1 The SRAM Address Decoder;75
8.2;4.2 Analysis of Resistive-Open Defects in the Address Decoder;77
8.3;4.3 Analysis and Test of ADOF;77
8.3.1;4.3.1 Functional Fault Modeling of ADOF;78
8.3.2;4.3.2 Experiments;80
8.3.2.1;4.3.2.1 Timing Constraints;83
8.3.3;4.3.3 March Test Solution Detecting ADOFs;85
8.3.3.1;4.3.3.1 Sachdev's Algorithm Converted in March Elements;87
8.3.3.2;4.3.3.2 March iC-;89
8.4;4.4 Conclusion;90
9;5 Resistive-Open Defects in Write Drivers;91
9.1;5.1 The SRAM Write Driver;91
9.1.1;5.1.1 Write Driver Within the I/O Circuitry;91
9.1.2;5.1.2 Operation Mode of the Write Driver;92
9.2;5.2 Analysis of Resistive-Open Defects in the Write Driver;94
9.2.1;5.2.1 Defect Location;94
9.2.2;5.2.2 Defect Incidence Analysis;95
9.2.3;5.2.3 Simulation Set-Up and Results;96
9.3;5.3 Analysis and Test of SWDF;97
9.3.1;5.3.1 Functional Fault Modeling of SWDF;97
9.3.2;5.3.2 Experiments;98
9.3.2.1;5.3.2.1 SWDF Due to Df5;98
9.3.2.2;5.3.2.2 SWDF Due to Df6;99
9.3.3;5.3.3 March Test Solution Detecting SWDFs;100
9.4;5.4 Analysis and Test of URWF/URDWF;102
9.4.1;5.4.1 Functional Fault Modeling of URDWF;102
9.4.2;5.4.2 Experiments;103
9.4.2.1;5.4.2.1 URDWF Due to Df9;103
9.4.2.2;5.4.2.2 URDWF vs. URWF;105
9.4.3;5.4.3 March Test Solution Detecting URDWFs;106
9.5;5.5 Conclusion;106
10;6 Resistive-Open Defects in Sense Amplifiers;108
10.1;6.1 The SRAM Sense Amplifier;108
10.1.1;6.1.1 Sense Amplifier Within the I/O Circuitry;108
10.1.2;6.1.2 Operation Mode of the Sense Amplifier;108
10.2;6.2 Analysis of Resistive-Open Defects in the Sense Amplifier;111
10.2.1;6.2.1 Defect Location;112
10.2.2;6.2.2 Defect Incidence Analysis;112
10.2.3;6.2.3 Simulation Set-Up and Results;113
10.3;6.3 Analysis and Test of d2cIRF1;114
10.3.1;6.3.1 Functional Fault Modeling of d2cIRF1;114
10.3.2;6.3.2 Experiments;115
10.3.3;6.3.3 March Test Solution Detecting d2cIRF1s;116
10.4;6.4 Analysis and Test of d2cIRF2;119
10.4.1;6.4.1 Functional Fault Modeling of d2cIRF2;119
10.4.2;6.4.2 Experiments;120
10.4.3;6.4.3 March Test Solution Detecting d2cIRF2s;121
10.5;6.5 d2cIRF1 vs. d2cIRF2;122
10.6;6.6 Conclusion;123
11;7 Faults Due to Process Variations in SRAMs;124
11.1;7.1 Influence of Threshold Voltage Deviations in SRAM Core-Cells;124
11.1.1;7.1.1 Simulation Flow;125
11.1.2;7.1.2 Mismatch Sensitivity During Read/Write Operations;125
11.1.3;7.1.3 V t Mismatch Related Fault Models;128
11.1.3.1;7.1.3.1 Result Overview;129
11.1.3.2;7.1.3.2 Test Requirements;130
11.2;7.2 Impact of Leakage Current of Core-Cell Pass-Transistors on the Read Operation;130
11.2.1;7.2.1 Analysis of Supply Voltage Variations;136
11.2.2;7.2.2 Analysis of Temperature Variations;137
11.2.3;7.2.3 Test and Diagnosis of LRFs;137
11.3;7.3 Complex Read Fault Analysis;139
11.4;7.4 Conclusion;141
12;8 Diagnosis and Design-for-Diagnosis;142
12.1;8.1 Diagnosis Methods;142
12.1.1;8.1.1 Cause--Effect Approach: Signature-Based Diagnosis;142
12.1.1.1;8.1.1.1 Principle;142
12.1.1.2;8.1.1.2 Extension to Dynamic Fault Diagnosis;143
12.1.2;8.1.2 Effect--Cause Approach: History-Based Diagnosis;146
12.1.2.1;8.1.2.1 Principle;147
12.1.2.2;8.1.2.2 Extension to Dynamic Fault Diagnosis;150
12.1.2.3;8.1.2.3 Experimental Results;156
12.2;8.2 Design-for-Diagnosis of Write Drivers;159
12.2.1;8.2.1 Requirements for Fault-Free Operations of a Write Driver;159
12.2.2;8.2.2 Description of the Current-Based DfD Solution;161
12.2.3;8.2.3 Description of the Voltage-Based DfD Solution;163
12.2.4;8.2.4 Diagnosis Sequence;166
12.3;8.3 Conclusion;167
13;Summary;168
14;References;171
15;Index;176