Birtwistle / Subrahmanyam Current Trends in Hardware Verification and Automated Theorem Proving

Erscheinungsjahr 2012
ISBN: 978-1-4612-3658-0
Verlag: Springer US
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 489 Seiten, eBook

This report describes the partially completed correctness proof of the Viper 'block model'. Viper [7,8,9,11,23] is a microprocessor designed by W. J. Cullyer, C. Pygott and J. Kershaw at the Royal Signals and Radar Establishment in Malvern, England, (henceforth 'RSRE') for use in safety-critical applications such as civil aviation and nuclear power plant control. It is currently finding uses in areas such as the de ployment of weapons from tactical aircraft. To support safety-critical applications, Viper has a particulary simple design about which it is relatively easy to reason using current techniques and models. The designers, who deserve much credit for the promotion of formal methods, intended from the start that Viper be formally verified. Their idea was to model Viper in a sequence of decreasingly abstract levels, each of which concentrated on some aspect ofthe design, such as the flow ofcontrol, the processingofinstructions, and so on. That is, each model would be a specification of the next (less abstract) model, and an implementation of the previous model (if any). The verification effort would then be simplified by being structured according to the sequence of abstraction levels. These models (or levels) of description were characterized by the design team. The first two levels, and part of the third, were written by them in a logical language amenable to reasoning and proof.

Zielgruppe

Research

Autoren/Hrsg.

Birtwistle, Graham

Subrahmanyam, P.A.

Inhaltsverzeichnis

1 Correctness Properties of the Viper Block Model: The Second Level.- 2 Formal Verification of the Sobel Image Processing Chip.- 3 Specification-Driven Design of Custom Hardware in HOP.- 4 Formal Verification of a Microprocessor Using Equational Techniques.- 5 OBJ as a Theorem Prover with Applications to Hardware Verification.- 6 Formal Verification in m-EVES.- 7 The Interactive Proof Editor: An Experiment in Interactive Theorem Proving.- 8 An Overview of the Edinburgh Logical Framework.- 9 Automating Recursive Type Definitions in Higher Order Logic.- 10 Mechanizing Programming Logics in Higher Order Logic.- 11 Automated Theorem Proving for Analysis and Synthesis of Computations.- 12 What Do Computer Architects Design Anyway?.