Low-Power Variation-Tolerant Design in Nanometer Silicon

1. Auflage. 2010
ISBN: 978-1-4419-7417-4
Verlag: Springer Us

Buch, Englisch, 440 Seiten, Format (B × H): 163 mm x 244 mm, Gewicht: 1800 g

Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.

Zielgruppe

Research

Autoren/Hrsg.

Bhunia, Swarup

Mukhopadhyay, Saibal

Fachgebiete

• Mathematik | Informatik EDV | Informatik Professionelle Anwendung Computer-Aided Design (CAD)
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise

Inhaltsverzeichnis

Introduction and Motivation.- Background on Power Dissipation.- Background on Parameter Variations.- Low power Logic Design under Variations.- Low Power Memory Design under Variations.- System and Architecture Level Design.- Emerging Challenges and Solution Approach.- Conclusion and Discussion.