Bhattacharyya / Deprettere / Teich Domain-Specific Processors

Systems, Architectures, Modeling, and Simulation
Erscheinungsjahr 2003
ISBN: 978-0-203-91318-5
Verlag: Taylor & Francis
Format: PDF
Kopierschutz: Adobe DRM (»Systemvoraussetzungen)

E-Book, Englisch, 280 Seiten

Reihe: Signal Processing and Communications

Ranging from low-level application and architecture optimizations to high-level modeling and exploration concerns, this authoritative reference compiles essential research on various levels of abstraction appearing in embedded systems and software design. It promotes platform-based design for improved system implementation and modeling and enhanced performance and cost analyses. Domain-Specific Processors relies upon notions of concurrency and parallelism to satisfy performance and cost constraints resulting from increasingly complex applications and architectures and addresses concepts in specification, simulation, and verification in embedded systems and software design.

Zielgruppe

Electrical, electronics, computer, communications, signal processing, and microprocessing engineers, and upper-level undergraduate and graduate students in these disciplines

Autoren/Hrsg.

Bhattacharyya, Shuvra S.

Deprettere, Ed F.

Teich, Jürgen

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Nachrichten- und Kommunikationstechnik
• Mathematik | Informatik EDV | Informatik EDV & Informatik Allgemein

Inhaltsverzeichnis

Automatic VHDL Model Generation of Parameterized FIR Filters, E.George Walters III, John Glossner, Michael J. Schulte; An LUT-Based High Level Synthesis Framework for Reconfigurable Architectures Lo c Lagadec, Bernard Pottier, and Oscar Villellas-Guillen; Highly Efficient Scalable Parallel-Pipelined Architectures for Discrete Wavelet Transforms David Guevorkian, Petri Liuha, Aki Launiainen and Ville Lappalainen; Stride Permutation Access in Interleaved Memory Systems, Jarmo Takala and Tuomas Jarvinen; Modelling of Intra-task Parallelism in Task-level Parallel Embedded Systems, Andy D. Pimentel, Frank P. Terpstra, Simon Polstra and Joe E. Coffland; Energy Estimation and Optimization for Piecewise Regular Processor Arrays, Frank Hannig and, Juergen Teich; Automatic Synthesis of Efficient Interfaces for Compiled Regular Architectures, Steven Derrien, Anne-Claire Quillou, Patrice Quinton, Tanguy Risset and Charles Wagner; Goal-Driven Reconfiguration of Polymorphous Architectures, Sumit Lohani and Shuvra S. Bhattacharyya; Realizations of the Extended Linearization Model, Alexandru Turjan, Bart Kienhuis, Ed Deprettere; Communication Services for Networks on Chip, Andrei Radulescu and Kees Goossens; Single chip Multiprocessing for Consumer Electronics, Paul Stravers and Jan Hoogerbugge; Future Directions of (Programmable and Reconfigurable) Embedded Processors, Stephan Wong, Stamatis Vassiliadis, Sorin Cotofana.