Bailey / Martin ESL Models and their Application

Electronic System Level Design and Verification in Practice
1. Auflage 2009
ISBN: 978-1-4419-0965-7
Verlag: Springer
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 446 Seiten

Reihe: Embedded Systems

This book arises from experience the authors have gained from years of work as industry practitioners in the field of Electronic System Level design (ESL). At the heart of all things related to Electronic Design Automation (EDA), the core issue is one of models: what are the models used for, what should the models contain, and how should they be written and distributed. Issues such as interoperability and tool transportability become central factors that may decide which ones are successful and those that cannot get sufficient traction in the industry to survive. Through a set of real examples taken from recent industry experience, this book will distill the state of the art in terms of System-Level Design models and provide practical guidance to readers that can be put into use. This book is an invaluable tool that will aid readers in their own designs, reduce risk in development projects, expand the scope of design projects, and improve developmental processes and project planning.

Autoren/Hrsg.

Bailey, Brian

Martin, Grant

Inhaltsverzeichnis

1;Preface;4
1.1; Who Should Read This Book;5
1.2;Structure of the Book;6
1.3;Chapter Listing;7
1.4;Relationship to First Book;9
1.5;Companion Web Site;9
1.6;Reference;10
2;Acknowledgments;11
3;Contents;12
4;About the Authors;18
5;About the Contributors;20
6;1 Introduction;22
6.1;1.1 A Definition of a Model;22
6.2;1.2 A Day in the Life of a Model;5
6.3;1.3 Types of Model;6
6.4;1.4 Models of Computation;7
6.5;1.5 Simplification;9
6.5.1;1.5.1 Abstraction;31
6.5.2;1.5.2 Structure;31
6.6;1.6 Models and Languages;33
6.6.1;1.6.1 Imperative Languages;33
6.6.2;1.6.2 Declarative Languages;34
6.6.3;1.6.3 Functional;35
6.6.4;1.6.4 Non-functional;36
6.6.5;1.6.5 Meta;37
6.6.6;1.6.6 Testbench;38
6.7;1.7 The Desire for a New Language;39
6.8;1.8 Big Shoes to Fill;40
6.8.1;1.8.1 Ptolemy Simulator;41
6.8.2;1.8.2 SystemC;42
6.8.3;1.8.3 Function and Interface;43
6.9;1.9 Taxonomy;43
6.9.1;1.9.1 Three New Axes;44
6.9.1.1;1.9.1.1 Concurrency;44
6.9.1.2;1.9.1.2 Communications;45
6.9.1.3;1.9.1.3 Configurability;45
6.9.2;1.9.2 Application to Models and Languages;46
6.9.3;1.9.3 Transformation of Models;48
6.10;1.10 Definitions;49
7;References;52
8;2 IP Meta-Models for SoC Assembly and HW/SW Interfaces;54
8.1;2.1 Introduction;54
8.2;2.2 IP Databases;54
8.3;2.3 SPIRIT/IP-XACT;55
8.3.1;2.3.1 History of SPIRIT;55
8.3.2;2.3.2 RTL Assembly Level;58
8.3.3;2.3.3 System Modeling Level;62
8.4;2.4 Register Definition Languages;62
8.4.1;2.4.1 Motivation: Modeling the HW/SW Interface;63
8.4.1.1;2.4.1.1 What Is the HW/SW Interface?;63
8.4.1.2;2.4.1.2 Hardware Configuration and Control Using Software;64
8.4.1.3;2.4.1.3 Software Perspective;65
8.4.1.4;2.4.1.4 Interrupts;67
8.4.1.5;2.4.1.5 Software API;67
8.4.1.6;2.4.1.6 Hardware Perspective;68
8.4.1.7;2.4.1.7 Transaction Bus Protocol;69
8.4.1.8;2.4.1.8 Protocol Translation;70
8.4.1.9;2.4.1.9 Registers and Bitfields;72
8.4.2;2.4.2 HW/SW Design Flow for HW/SW Interfaces;77
8.4.2.1;2.4.2.1 Example IP Design -- The Requirements;78
8.4.2.2;2.4.2.2 Specification -- Documentation;79
8.4.2.3;2.4.2.3 IP-XACT (SPIRIT);79
8.4.2.4;2.4.2.4 SystemRDL;81
8.4.2.5;2.4.2.5 IP Hardware Design;81
8.4.2.6;2.4.2.6 IP Verification;84
8.4.2.7;2.4.2.7 HDL Verification Environments;85
8.4.2.8;2.4.2.8 HVL Environments;85
8.4.2.9;2.4.2.9 VMM -- Verification Methodology Manual;86
8.4.2.10;2.4.2.10 OVM -- Open Verification Methodology;87
8.4.2.11;2.4.2.11 eRM '' Specman ''e'' Reuse Methodology;88
8.4.2.12;2.4.2.12 OVM vs. VMM Interoperability;88
8.4.2.13;2.4.2.13 Chip-Level Verification;88
8.4.2.14;2.4.2.14 Software Development -- Firmware;91
8.4.2.15;2.4.2.15 Firmware Verification;93
8.4.2.16;2.4.2.16 RTL Models;94
8.4.2.17;2.4.2.17 Virtual Models;94
8.4.2.18;2.4.2.18 Earlier Software Development;94
8.4.3;2.4.3 Emerging HW/SW Interface Tools and Design Flows;95
8.4.3.1;2.4.3.1 Register Management Tools;96
8.4.3.2;2.4.3.2 Case Study of a Register Management Solution: Bitwise;98
8.5;2.5 Conclusions;101
8.6;References;102
9;3 Functional Models;104
9.1;3.1 Dynamic Models and Languages;104
9.1.1;3.1.1 Algorithmic Languages;105
9.1.1.1;3.1.1.1 Mathematical Modeling Languages;105
9.1.1.2;3.1.1.2 Example of MATLAB;106
9.1.1.3;3.1.1.3 Example of C/C++ Reference Model;108
9.1.1.4;3.1.1.4 Dataflow Modeling Languages;109
9.1.1.5;3.1.1.5 Example of Simulink;110
9.1.2;3.1.2 Architectural Modeling Languages: SystemC;112
9.1.2.1;3.1.2.1 Scope of SystemC: Design Problems;112
9.1.2.2;3.1.2.2 SystemC 2.0;114
9.1.2.3;3.1.2.3 SystemC Language Basics;114
9.1.2.4;3.1.2.4 SystemC in Real Systems;122
9.1.2.5;3.1.2.5 Software System Specification;134
9.1.2.6;3.1.2.6 TLM 2.0;138
9.1.2.7;3.1.2.7 TLM Compliance Checking;149
9.1.3;3.1.3 Architectural Models;155
9.1.3.1;3.1.3.1 Modeling IP;155
9.1.3.2;3.1.3.2 System Models for Architectural Exploration;156
9.1.3.3;3.1.3.3 System Models for Software Development;158
9.2;3.2 Formal Models;158
9.2.1;3.2.1 Property Languages;158
9.2.1.1;3.2.1.1 Uses of Declarative Languages;159
9.2.1.2;3.2.1.2 Completeness;160
10;References;162
11;4 Testbench Models;163
11.1;4.1 Testbench Basics;164
11.1.1;4.1.1 Testbench Components;166
11.1.1.1;4.1.1.1 Verification Plan;167
11.1.1.2;4.1.1.2 Comparison Model;167
11.1.1.3;4.1.1.3 Progress Model;168
11.1.1.4;4.1.1.4 Input Constraints Model;168
11.1.2;4.1.2 Verification Methodologies;169
11.1.3;4.1.3 Verification IP;172
11.2;4.2 Verification Plan;172
11.3;4.3 Comparison Model;177
11.3.1;4.3.1 Testbench Languages;178
11.4;4.4 Progress Model;181
11.4.1;4.4.1 Ad Hoc Metrics;181
11.4.2;4.4.2 Structural Metrics;181
11.4.3;4.4.3 Functional Metrics;182
11.4.4;4.4.4 Coverage Metrics in SystemC;182
11.4.4.1;4.4.4.1 Simple Code Coverage;183
11.4.4.2;4.4.4.2 SystemC Verification Library;183
11.4.5;4.4.5 Coverage Metrics in SystemVerilog;185
11.5;4.5 Input Constraints;186
11.6;4.6 Verification IP;188
11.6.1;4.6.1 VIP Components;189
11.6.2;4.6.2 VIP Standardization;190
11.7;4.7 Conclusions;190
11.8;References;191
12;5 Virtual Prototypes and Mixed Abstraction Modeling;193
12.1;5.1 Introduction;195
12.1.1;5.1.1 Historical Perspective;196
12.1.2;5.1.2 Use Models;199
12.1.2.1;5.1.2.1 Early Verification and Validation;199
12.1.2.2;5.1.2.2 Architectural Analysis;200
12.1.2.3;5.1.2.3 Software Development;201
12.1.2.4;5.1.2.4 Debug and Visibility;202
12.1.3;5.1.3 Technology;203
12.1.3.1;5.1.3.1 Taxonomy;203
12.1.3.2;5.1.3.2 Time Advancement;207
12.1.4;5.1.4 Interfaces;207
12.1.5;5.1.5 Processor Models;208
12.2;5.2 System Prototypes;211
12.2.1;5.2.1 Development Environments for Software Development;211
12.2.2;5.2.2 Hybrid Hardware--Software-Based Development Platforms;213
12.2.3;5.2.3 Hybrid System Prototyping Use Models;214
12.3;5.3 Constructing a System-Level Virtual Prototype;214
12.3.1;5.3.1 Modeling Languages;216
12.3.1.1;5.3.1.1 SystemC;216
12.3.1.2;5.3.1.2 Magic-C;217
12.3.1.3;5.3.1.3 VRE C++;219
12.3.2;5.3.2 Model Creation;220
12.3.3;5.3.3 Model Import;221
12.3.4;5.3.4 Model Libraries;221
12.3.5;5.3.5 Virtual Devices;222
12.3.6;5.3.6 Modeling the Environment;224
12.3.7;5.3.7 Tying It All Together;225
12.3.8;5.3.8 Documentation;225
12.4;5.4 Running the Prototype;225
12.4.1;5.4.1 Debug;227
12.4.2;5.4.2 Analysis;228
12.4.2.1;5.4.2.1 Power Analysis;233
12.5;5.5 Verification;234
12.5.1;5.5.1 Platform Deployment;234
12.5.2;5.5.2 Verification Methodology Manual;235
12.5.3;5.5.3 Building the RTL Testbench;236
12.5.4;5.5.4 Regressions;237
12.6;5.6 Example;238
12.6.1;5.6.1 The Application;239
12.6.2;5.6.2 The Bottom Line;242
12.7;5.7 The Future;243
13;References;244
14;6 Processor-Centric Design: Processors, Multi-Processors, and Software;245
14.1;6.1 Choices and Trade-Offs in Processor-Centric Design;245
14.2;6.2 An ASIP Integrated Development Environment (IDE);249
14.3;6.3 Introduction to Flow and Example;252
14.4;6.4 Starting with Algorithms;254
14.5;6.5 Processor Definition;254
14.5.1;6.5.1 Designing the Design Space Exploration;254
14.5.2;6.5.2 Exploring the Processor Design Space: Preconfigured Cores;256
14.5.3;6.5.3 Exploring the Processor Design Space: Automatically;260
14.5.4;6.5.4 Exploring the Processor Design Space: Cache and Memory;268
14.5.5;6.5.5 Exploring the Processor Design Space: Fine-Tuning;269
14.5.6;6.5.6 Speed--Area--Power Trade-offs;272
14.5.7;6.5.7 Detailed Energy Space Exploration;275
14.6;6.6 Software Implementation;276
14.7;6.7 Predicting Software Performance via Sampling;278
14.8;6.8 Multicore Issues;279
14.8.1;6.8.1 A Practical Methodology for Multi-processor ASIP Definition and Programming;282
14.8.2;6.8.2 Developing Multicore System-Level Models;285
14.8.3;6.8.3 Porting Methodology for New Video Codecs to the Multicore system;285
14.8.4;6.8.4 Using the IDE for Multicore Simulation and Validation;287
14.9;6.9 Debug;288
14.9.1;6.9.1 Single-Core Debug in the IDE;288
14.9.2;6.9.2 Multi-processor Debug in the IDE;288
14.10;6.10 Conclusions;292
15;References;292
16;7 Codesign Experiences Based on a Virtual Platform;293
16.1;7.1 Introduction;293
16.2;7.2 Virtual Platforms;294
16.2.1;7.2.1 Introduction;294
16.2.2;7.2.2 Evolution of Platform Complexity;294
16.2.3;7.2.3 Methodologies;295
16.2.4;7.2.4 Commercial Technologies for Virtual Platform Development;297
16.2.5;7.2.5 Models of Computation;300
16.3;7.3 Platform and Application Description;300
16.3.1;7.3.1 System Specification and Functional Verification;302
16.3.2;7.3.2 Architectural Exploration;304
16.3.2.1;7.3.2.1 Definition and Configuration;305
16.3.2.2;7.3.2.2 Moving Modules Between Hardware and Software Partitions on a Multi-bus Architecture;308
16.3.2.3;7.3.2.3 ISS Abstraction;309
16.3.3;7.3.3 Analysis;312
16.3.3.1;7.3.3.1 User Module Computation and RTOS Computation;314
16.3.3.2;7.3.3.2 User Module Communication;315
16.3.3.3;7.3.3.3 Bus Usage;315
16.3.4;7.3.4 Integration;317
16.3.4.1;7.3.4.1 Interface Synthesis;317
16.3.4.2;7.3.4.2 Behavioral Synthesis;317
16.3.4.3;7.3.4.3 Platform Synthesis;319
16.4;7.4 Experiments;320
16.4.1;7.4.1 Pipelined vs. Non-pipelined Models;320
16.4.2;7.4.2 Architectural Exploration of the JPEG Decoder;322
16.5;7.5 Conclusion;325
16.6;References;327
17;8 Transaction-Level Platform Creation;329
17.1;8.1 Introduction;329
17.2;8.2 Transaction-Level Modeling Comes of Age;330
17.3;8.3 Model Abstractions;332
17.3.1;8.3.1 Terminology;332
17.3.2;8.3.2 Model Taxonomy;333
17.4;8.4 Roles of the TLM Platform;335
17.5;8.5 Contextual Verification;337
17.6;8.6 Creating Models;339
17.6.1;8.6.1 Model Refinement;340
17.6.2;8.6.2 Multi-abstraction;343
17.6.2.1;8.6.2.1 SystemVerilog DPI;344
17.6.2.2;8.6.2.2 Transactor Models;344
17.6.3;8.6.3 Verification;345
17.6.3.1;8.6.3.1 Verifying the System Model;346
17.6.3.2;8.6.3.2 Using the System Model for RTL Verification;347
17.7;8.7 Timing;353
17.7.1;8.7.1 Timing Policies;355
17.7.2;8.7.2 Delay;355
17.7.3;8.7.3 Split;356
17.7.4;8.7.4 Sequential;357
17.7.5;8.7.5 Pipelining;358
17.7.6;8.7.6 Putting It All Together;359
17.7.7;8.7.7 Timing Callbacks;361
17.8;8.8 Power;362
17.9;8.9 Creating a Model;362
17.9.1;8.9.1 Using Model Builder;362
17.9.2;8.9.2 Synchronization;365
17.9.3;8.9.3 Integrating 3rd party Models;366
17.9.4;8.9.4 Model Abstraction;366
17.9.5;8.9.5 Building a System;366
17.9.6;8.9.6 Navigating a System;367
17.10;8.10 Example;368
17.10.1;8.10.1 Building the System;370
17.10.2;8.10.2 Running the Simulation;371
17.10.3;8.10.3 Analyzing the System;374
17.10.4;8.10.4 Inserting an ISS Model;376
17.11;8.11 Conclusions;378
17.12;References;379
18;9 C/C++ Hardware Design for the Real World;380
18.1;9.1 Introduction;380
18.1.1;9.1.1 Chapter Overview;381
18.2;9.2 Where Does It Fit in an ESL Flow;382
18.2.1;9.2.1 Hardware Implementation Input;384
18.2.2;9.2.2 High-Level Synthesis Output;386
18.2.3;9.2.3 Verification Models;387
18.2.4;9.2.4 Other Uses for the Input Model;388
18.3;9.3 Why C/C++/SystemC;388
18.3.1;9.3.1 Language Limitations for Synthesis;391
18.4;9.4 High-Level Synthesis Fundamentals;392
18.4.1;9.4.1 Schedule and Allocation Trade-offs;392
18.4.2;9.4.2 Synthesis at the Interface;394
18.4.3;9.4.3 Hierarchy;394
18.4.4;9.4.4 Other Control;395
18.4.5;9.4.5 Target Library;397
18.4.6;9.4.6 Data-Type Libraries for Synthesis;397
18.4.7;9.4.7 Synthesis Tools;401
18.4.7.1;9.4.7.1 The Gantt Chart;401
18.4.7.2;9.4.7.2 Datapath Diagram;402
18.4.7.3;9.4.7.3 Interactive Exploration;403
18.5;9.5 Synthesis Domains;403
18.6;9.6 A Simple Example;404
18.6.1;9.6.1 Embedded Architecture;405
18.7;9.7 Tying It into a Verification Flow;411
18.7.1;9.7.1 Verification with Simulation;411
18.7.2;9.7.2 Verification with Equivalence Checking;413
18.7.3;9.7.3 Verification Against Algorithmic Model;413
18.7.4;9.7.4 Verifying Power;415
18.8;9.8 A More Complex Example;415
18.8.1;9.8.1 The Application;417
18.8.2;9.8.2 The Flow;418
18.8.3;9.8.3 Design;419
18.8.3.1;9.8.3.1 Step 1: Research Phase;419
18.8.3.2;9.8.3.2 Step 2: Pick a Solution;419
18.8.3.3;9.8.3.3 Step 3: Code the Algorithm;421
18.8.3.4;9.8.3.4 Step 4: Taking Care with I/O Ports;427
18.8.3.5;9.8.3.5 Step 5: Dealing with the Inverse Square Root;430
18.8.4;9.8.4 Verification;434
18.8.5;9.8.5 Synthesis;436
18.8.5.1;9.8.5.1 Synthesizing the Square Root;436
18.8.5.2;9.8.5.2 Manipulating Variables and Resources;437
18.8.5.3;9.8.5.3 Synthesizing the QR Block;438
18.8.6;9.8.6 Results;442
18.8.7;9.8.7 Results Analysis;444
18.9;9.9 Successful Adoption;445
18.10;9.10 The Future;447
18.11;9.11 Summary;448
18.12;References;449
19;Acronyms;452
20;Index;456