Low Power RF Circuit Design in Standard CMOS Technology

2012
ISBN: 978-3-642-26962-2
Verlag: Springer

Buch, Englisch, 236 Seiten, Previously published in hardcover, Format (B × H): 155 mm x 235 mm, Gewicht: 394 g

Reihe: Lecture Notes in Electrical Engineering

Low Power Consumption is one of the critical issues in the performance of small battery-powered handheld devices. Mobile terminals feature an ever increasing number of wireless communication alternatives including GPS, Bluetooth, GSM, 3G, WiFi or DVB-H. Considering that the total power available for each terminal is limited by the relatively slow increase in battery performance expected in the near future, the need for efficient circuits is now critical. This book presents the basic techniques available to design low power RF CMOS analogue circuits. It gives circuit designers a complete guide of alternatives to optimize power consumption and explains the application of these rules in the most common RF building blocks: LNA, mixers and PLLs. It is set out using practical examples and offers a unique perspective as it targets designers working within the standard CMOS process and all the limitations inherent in these technologies.

Zielgruppe

Research

Autoren/Hrsg.

Alvarado, Unai

Adín, Iñigo

Bistué, Guillermo

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Nachrichten- und Kommunikationstechnik Funktechnik
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Schaltungsentwurf

Inhaltsverzeichnis

Introduction.- Power Considerations in Analog Rf CMOS Circuits.- Impact of Architecture Selection on RF Front-End Power Consumption.- Technology Structural Alternatives in Standard CMOS Technologies for Low-Power Analog Design.- Schematic Design Techniques for Power Saving in RF.- RF Amplifier Design.- Mixer Design.- Phase Locked Loop (PLL) Design.