Abbas Handbook of Digital CMOS Technology, Circuits, and Systems

1. Auflage 2020
ISBN: 978-3-030-37195-1
Verlag: Springer International Publishing
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 653 Seiten

This book provides a comprehensive reference for everything that has to do with digital circuits.  The author focuses equally on all levels of abstraction.  He tells a bottom-up story from the physics level to the finished product level. The aim is to provide a full account of the experience of designing, fabricating, understanding, and testing a microchip. The content is structured to be very accessible and self-contained, allowing readers with diverse backgrounds to read as much or as little of the book as needed. Beyond a basic foundation of mathematics and physics, the book makes no assumptions about prior knowledge. This allows someone new to the field to read the book from the beginning. It also means that someone using the book as a reference will be able to answer their questions without referring to any external sources.

Karim Abbas received his Ph.D. in electrical engineering from UCLA in 2009. Since then he has been an assistant professor at Cairo University in Cairo, Egypt.  His main area of interest is the intersection of systems level design and digital circuits design.  He has been doing research on and teaching digital circuit design for nineteen years.

Autoren/Hrsg.

Abbas, Karim

Inhaltsverzeichnis

1;Preface;6
1.1;There’s Something About Electronics;6
1.2;The Signals We Give;7
1.2.1;Analog Circuits;7
1.2.2;Digital Circuits;8
1.2.3;Mixed-Signal Circuits;9
1.3;It’s an Abstract Art;10
1.4;What is This All About?;12
1.5;How to Use This Book;17
1.6;Assumptions, Simplifications, Accuracy, and Managing to Do Anything;19
1.7;The Formula of the Book;20
1.8;The Story as It Is Told;20
2;Contents;23
3;1 Devices;27
3.1;1.1 The Band Model;27
3.2;1.2 Intrinsic Silicon;32
3.3;1.3 Band Model with Doping;36
3.4;1.4 Extrinsic Silicon;40
3.5;1.5 Drift;43
3.6;1.6 Diffusion;47
3.7;1.7 Forming a Homojunction;49
3.8;1.8 PN Junction in Equilibrium;52
3.9;1.9 Junction Capacitance;55
3.10;1.10 Forward and Reverse Bias;57
3.11;1.11 Minority Carrier Injection;59
3.12;1.12 Forward-Biased PN Junction Current;61
3.13;1.13 Bipolar Junction Transistor;67
3.14;1.14 Materials Interfaces;75
3.15;1.15 MOS Capacitor Preliminaries;81
3.16;1.16 Modes of the MOS Capacitor;84
3.17;1.17 MOS Capacitor Characteristics;91
3.18;1.18 MOSFET Linear Regime;93
3.19;1.19 MOSFET Saturation Regime;94
3.20;1.20 Body Effect;100
3.21;1.21 Channel Length Modulation;103
4;2 Ratioed Logic;106
4.1;2.1 PMOS;106
4.2;2.2 Regions of the MOSFET;107
4.3;2.3 BJT Logic;110
4.4;2.4 Abandoning BJT;110
4.5;2.5 Scaling MOSFET;113
4.6;2.6 What is a Logic Family;115
4.7;2.7 Resistive Load Inverter;118
4.8;2.8 Open-Circuited Transistor;120
4.9;2.9 Enhancement Load Inverter;121
4.10;2.10 Enhancement Load VTC;122
4.11;2.11 Static Power;123
4.12;2.12 NAND and NOR Enhancement Load;124
4.13;2.13 Random Logic in Enhancement Load;128
4.14;2.14 Depletion Load Logic;129
4.15;2.15 Pseudo-NMOS Logic;131
4.16;2.16 Limitations of Ratioed Logic;132
5;3 CMOS;135
5.1;3.1 Basics of the CMOS Inverter;135
5.2;3.2 CMOS VTC;136
5.3;3.3 Preliminaries of Delay;140
5.4;3.4 MOS Capacitance and Resistance;144
5.5;3.5 Simplified Delay Model;147
5.6;3.6 Non-static Power;149
5.7;3.7 CMOS NAND and NOR;152
5.8;3.8 CMOS Complex Logic;154
5.9;3.9 Sizing, Delay, and Area;159
5.10;3.10 Supply and Width Scaling;165
5.11;3.11 Limitations of CMOS;166
6;4 Logical Effort;168
6.1;4.1 Sizing in a Chain;168
6.2;4.2 Sizing an Inverter Chain;168
6.3;4.3 Gates Versus Inverters: Preliminaries;171
6.4;4.4 Normalizing Gate Intrinsic Delay;172
6.5;4.5 Normalizing Gate External Delay;173
6.6;4.6 Architecture, Inputs, and Effort;175
6.7;4.7 Optimal Sizing in a Logic Chain;176
6.8;4.8 Logical Effort for Multiple Inputs;179
7;5 Dynamic Logic;180
7.1;5.1 High-Impedance Nodes;180
7.2;5.2 Dynamic CMOS and Why it is Great;181
7.3;5.3 Delay, Period, and Duty Cycle;185
7.4;5.4 Leakage in Dynamic Logic;185
7.5;5.5 Charge Sharing;190
7.6;5.6 Cascading Dynamic Logic;194
7.7;5.7 Logical Effort in Dynamic Gates;198
8;6 Pipelines;200
8.1;6.1 Sequential Versus Combinational;200
8.2;6.2 Latches, Registers, and Timing;203
8.3;6.3 The Static Register;204
8.4;6.4 Dynamic Registers;210
8.5;6.5 Imperfect Clocks and Hold-Time;211
8.6;6.6 Pipelines, Critical Path, and Slack;215
8.7;6.7 Managing Power in a Pipeline;222
8.8;6.8 Examples on Pipelining;228
8.9;6.9 Impact of Variations;236
9;7 CMOS Process;239
9.1;7.1 Setting and Location;239
9.2;7.2 Photolithography Iteration;241
9.3;7.3 Account of Materials;243
9.4;7.4 Wafer Fabrication;245
9.5;7.5 Operations and Equipment;248
9.6;7.6 Locos;259
9.7;7.7 Advanced Issues in CMOS Processing;269
9.8;7.8 Account of Layers;293
10;8 Design Flow;296
10.1;8.1 What Is a Layout;296
10.2;8.2 Stick Diagrams;297
10.3;8.3 Standard Cells;301
10.4;8.4 Design Rules: Foundations;309
10.5;8.5 Design Rules—Sample;313
10.6;8.6 Fixed-Point Simulation;319
10.7;8.7 Physical Design;324
10.8;8.8 FPGAs;333
11;9 HDL;338
11.1;9.1 Design Philosophy;338
11.2;9.2 The Entity;340
11.3;9.3 IEEE Library and std_logic;340
11.4;9.4 Types, Attributes, and Operators;343
11.5;9.5 Architecture;348
11.6;9.6 Structural Connections;348
11.7;9.7 Generics and Constants;356
11.8;9.8 Multiplexing and Choice;363
11.9;9.9 The Process Statement;363
11.10;9.10 Signals and Variables;366
11.11;9.11 Selection in a Process;368
11.12;9.12 Latches and Implicit Latches;369
11.13;9.13 Registers and Pipelines;378
11.14;9.14 Memories;386
11.15;9.15 Counters;390
11.16;9.16 State Machines;394
11.17;9.17 Testbenches—Preliminaries;400
11.18;9.18 Functions and Procedures;402
11.19;9.19 Wait, Assertions, and Loops;408
11.20;9.20 File I/Os;415
11.21;9.21 Packages and Configurations;422
11.22;9.22 Good Design Practices;426
12;10 Scaling;431
12.1;10.1 Steep Retrograde Body Effect;431
12.2;10.2 Velocity Saturation;432
12.3;10.3 MOSFET Leakage;436
12.4;10.4 DIBL;442
12.5;10.5 MOSFET Structures for DIBL;447
12.6;10.6 Miscellaneous Scaling Effects;450
12.7;10.7 Impacts on CMOS;455
13;11 Arithmetic;459
13.1;11.1 Binary Addition and Full Adders;459
13.2;11.2 Ripple Carry Adder;461
13.3;11.3 Generate—Propagate Logic;462
13.4;11.4 Carry-Save and Bypass Adders;465
13.5;11.5 Lookahead Addition;469
13.6;11.6 Group Generates and Propagates;471
13.7;11.7 Parallel Prefix Adders;473
13.8;11.8 Binary Multiplication;476
13.9;11.9 Array Multipliers;477
13.10;11.10 Wallace and DADDA Multipliers;479
13.11;11.11 Booth Multiplication;484
14;12 Memories;490
14.1;12.1 Architectures and Definitions;490
14.2;12.2 NOR ROM Arrays;493
14.3;12.3 NAND ROM Arrays;498
14.4;12.4 NVMs;501
14.5;12.5 SRAM Cell;511
14.6;12.6 Sense Amplifiers;515
14.7;12.7 SRAM Timing;519
14.8;12.8 DRAM Cells;523
14.9;12.9 Decoders and Buffers;529
15;13 Wires and Clocks;538
15.1;13.1 Basics;538
15.2;13.2 Lumped C Wires;541
15.3;13.3 Silicon Wires;543
15.4;13.4 Scaling Wires;544
15.5;13.5 Interchip Communication;546
15.6;13.6 Supply and Ground;552
15.7;13.7 Clock Networks;555
15.8;13.8 Metastability;559
15.9;13.9 Synchronization;565
16;14 Testing;570
16.1;14.1 Fundamentals of Testing;570
16.2;14.2 Logical Hazards;578
16.3;14.3 Stuck-at Fault Model;586
16.4;14.4 Scan Paths;590
16.5;14.5 Built in Self-test;595
16.6;14.6 IC Packaging and Boundary Scan;599
16.7;14.7 Testing Memories;605
16.8;14.8 Reliability;608
17;Glossary;611
18;Index;651