Guessing Random Additive Noise Decoding

A Hardware Perspective
2023
ISBN: 978-3-031-31662-3
Verlag: Springer Nature Switzerland

Buch, Englisch, 151 Seiten, Format (B × H): 215 mm x 285 mm, Gewicht: 680 g

This book gives a detailed overview of a universal Maximum Likelihood (ML) decoding technique, known as Guessing Random Additive Noise Decoding (GRAND), has been introduced for short-length and high-rate linear block codes. The interest in short channel codes and the corresponding ML decoding algorithms has recently been reignited in both industry and academia due to emergence of applications with strict reliability and ultra-low latency requirements . A few of these applications include Machine-to-Machine (M2M) communication, augmented and virtual Reality, Intelligent Transportation Systems (ITS), the Internet of Things (IoTs), and Ultra-Reliable and Low Latency Communications (URLLC), which is an important use case for the 5G-NR standard.

GRAND features both soft-input and hard-input variants. Moreover, there are traditional GRAND variants that can be used with any communication channel, and specialized GRAND variants that are developed for a specific communication channel. This book presents a detailed overview of these GRAND variants and their hardware architectures.

The book is structured into four parts. Part 1 introduces linear block codes and the GRAND algorithm. Part 2 discusses the hardware architecture for traditional GRAND variants that can be applied to any underlying communication channel. Part 3 describes the hardware architectures for specialized GRAND variants developed for specific communication channels. Lastly, Part 4 provides an overview of recently proposed GRAND variants and their unique applications.

This book is ideal for researchers or engineers looking to implement high-throughput and energy-efficient hardware for GRAND, as well as seasoned academics and graduate students interested in the topic of VLSI hardware architectures. Additionally, it can serve as reading material in graduate courses covering modern error correcting codes and Maximum Likelihood decoding for short codes.

Zielgruppe

Research

Autoren/Hrsg.

Abbas, Syed Mohsin

Gross, Warren J.

Jalaleddine, Marwan

Fachgebiete

• Mathematik | Informatik EDV | Informatik Daten / Datenbanken Informationstheorie, Kodierungstheorie
• Interdisziplinäres Wissenschaften Wissenschaften: Forschung und Information Informationstheorie, Kodierungstheorie
• Technische Wissenschaften Elektronik | Nachrichtentechnik Nachrichten- und Kommunikationstechnik
• Mathematik | Informatik EDV | Informatik Technische Informatik Hardware: Grundlagen und Allgemeines

Inhaltsverzeichnis

Guessing Random Additive Noise Decoding (GRAND).- Hardware Architecture for GRAND with ABandonment (GRANDAB).- Hardware Architecture for Ordered Reliability Bits GRAND (ORBGRAND).- Hardware Architecture for List GRAND (LGRAND).- Hardware Architecture for GRAND Markov Order (GRAND-MO).- Hardware Architecture for Fading-GRAND.- A survey of recent GRAND variants.

Über Autor(innen)

Syed Mohsin Abbas is a postdoctoral researcher at Integrated Systems for Information Processing (ISIP) Lab at McGill University, Canada. He received his PhD. from the Department of Electronics and Computer Engineering (ECE) at the Hong Kong University of Science and Technology (HKUST). Dr. Abbas's research interests include the development of high-throughput and energy-efficient VLSI architectures for modern channel code decoders. In addition, his curiosity is fueled by topics such as information theory, VLSI Design, Computer Architecture, Embedded Systems, Massive MIMO, and 5G/6G communication.

Marwan Jalaleddine is a PhD. candidate and teaching assistant at McGill University. His research interests lie in modern Error Correcting Codes (ECCs) and their application in wireless communication technology.

Warren J. Gross is a James McGill Professor and the Chair of the Department of Electrical and Computer Engineering at McGill University,Montreal, QC, Canada. He received the PhD degree from the University of Toronto. His research interests are in the design and implementation of signal processing systems and custom computer architectures. He served as the Chair of the IEEE Signal Processing Society Technical Committee on Design and Implementation of Signal Processing Systems. He has served as a General Chair and Technical Program Chair of several conferences and workshops. He served as an Associate Editor for the IEEE Transactions on Signal Processing and as a Senior Area Editor.