Buch, Englisch, Band 9, 230 Seiten, Paperback, Format (B × H): 156 mm x 234 mm, Gewicht: 383 g
Logic Synthesis and Verification Using Testing Techniques
Buch, Englisch, Band 9, 230 Seiten, Paperback, Format (B × H): 156 mm x 234 mm, Gewicht: 383 g
Reihe: Frontiers in Electronic Testing
ISBN: 978-1-4419-5176-2
Verlag: Springer US
While Boolean reasoning techniques have been a central element of two-level circuit theory for many decades Reasoning in Boolean Networks describes a basic reasoning methodology for multi-level circuits. This leads to a unified view on two-level and multi-level logic synthesis. The presented reasoning techniques are applied to various CAD-problems to demonstrate their usefulness for today's industrially relevant problems.
Reasoning in Boolean Networks provides lucid descriptions of basic algorithmic concepts in automatic test pattern generation, logic synthesis and verification and elaborates their intimate relationship to provide further intuition and insight into the subject. Numerous examples are provide for ease in understanding the material.
Reasoning in Boolean Networks is intended for researchers in logic synthesis, VLSI testing and formal verification as well as for integrated circuit designers who want to enhance their understanding of basic CAD methodologies.
Zielgruppe
Research
Autoren/Hrsg.
Fachgebiete
- Geisteswissenschaften Design Produktdesign, Industriedesign
- Technische Wissenschaften Technik Allgemein Computeranwendungen in der Technik
- Mathematik | Informatik EDV | Informatik Informatik
- Mathematik | Informatik EDV | Informatik Angewandte Informatik Computeranwendungen in Wissenschaft & Technologie
- Mathematik | Informatik EDV | Informatik Professionelle Anwendung Computer-Aided Design (CAD)
- Technische Wissenschaften Technik Allgemein Konstruktionslehre und -technik
- Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
Weitere Infos & Material
1 Preliminaries.- 2 Combinational Atpg.- 3 Recursive Learning.- 4 AND/OR Reasoning Graphs.- 5 Logic Optimization.- 6 Logic Verification.- 7 Conclusions and Future Work.- References.