Buch, Englisch, Band 5470, 327 Seiten, Format (B × H): 155 mm x 235 mm, Gewicht: 524 g
Buch, Englisch, Band 5470, 327 Seiten, Format (B × H): 155 mm x 235 mm, Gewicht: 524 g
Reihe: Lecture Notes in Computer Science
ISBN: 978-3-642-00903-7
Verlag: Springer
caches.Theyintroduce a reuse-distance drowsy cache mechanism that issimpleas well as e?ective in reducingthestaticpower in caches.
Zielgruppe
Research
Autoren/Hrsg.
Fachgebiete
- Mathematik | Informatik EDV | Informatik Programmierung | Softwareentwicklung Algorithmen & Datenstrukturen
- Mathematik | Informatik EDV | Informatik Technische Informatik Hochleistungsrechnen, Supercomputer
- Mathematik | Informatik EDV | Informatik Technische Informatik Externe Speicher & Peripheriegeräte
- Mathematik | Informatik EDV | Informatik Informatik Logik, formale Sprachen, Automaten
- Mathematik | Informatik EDV | Informatik Informatik Rechnerarchitektur
- Mathematik | Informatik EDV | Informatik Technische Informatik Netzwerk-Hardware
- Mathematik | Informatik EDV | Informatik Programmierung | Softwareentwicklung Programmier- und Skriptsprachen
- Mathematik | Informatik EDV | Informatik Programmierung | Softwareentwicklung Prozedurale Programmierung
Weitere Infos & Material
Special Section on High-Performance Embedded Architectures and Compilers.- Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches.- Compiler-Assisted Memory Encryption for Embedded Processors.- Branch Predictor Warmup for Sampled Simulation through Branch History Matching.- Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems.- Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization.- Regular Papers.- Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors.- Fetch Gating Control through Speculative Instruction Window Weighting.- Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers.- Linux Kernel Compaction through Cold Code Swapping.- Complexity Effective Bypass Networks.- A Context-Parameterized Model for Static Analysis of Execution Times.- Reexecution and Selective Reuse in Checkpoint Processors.- Compiler Support for Code Size Reduction Using a Queue-Based Processor.- Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC.- Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories.
