High-Speed CMOS Circuits for Optical Receivers

2001
ISBN: 978-0-7923-7388-9
Verlag: Springer US

Buch, Englisch, 124 Seiten, HC runder Rücken kaschiert, Format (B × H): 160 mm x 241 mm, Gewicht: 386 g

With the exponential growth of the number of Internet nodes, the volume of the data transported on the backbone has increased with the same trend. The load of the global Internet backbone will soon increase to tens of terabits per second. This indicates that the backbone bandwidth requirements will increase by a factor of 50 to 100 every seven years. Transportation of such high volumes of data requires suitable media with low loss and high bandwidth. Among the available transmission media, optical fibers achieve the best performance in terms of loss and bandwidth. High-speed data can be transported over hundreds of kilometers of single-mode fiber without significant loss in signal integrity. These fibers progressively benefit from reduction of cost and improvement of perf- mance. Meanwhile, the electronic interfaces used in an optical network are not capable of exploiting the ultimate bandwidth of the fiber, limiting the throughput of the network. Different solutions at both the system and the circuit levels have been proposed to increase the data rate of the backbone. System-level solutions are based on the utilization of wave-division multiplexing (WDM), using different colors of light to transmit s- eral sequences simultaneously. In parallel with that, a great deal of effort has been put into increasing the operating rate of the electronic transceivers using highly-developed fabrication processes and novel c- cuit techniques.

Zielgruppe

Research

Autoren/Hrsg.

Razavi, Behzad

Savoj, Jafar

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Halb- und Supraleitertechnologie
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise

Inhaltsverzeichnis

TIAs and Limiters.- Clock and Data Recovery Architectures.- A CMOS Interface for Detection of 1.2-Gb / s RZ Data.- A 10-Gb/s Linear Half-rate CMOS CDR Circuit.- A 10-Gb/s CMOS CDR Circuit with Wide Capture Range.- Conclusion.