High-Level Power Analysis and Optimization

1998
ISBN: 978-0-7923-8073-3
Verlag: Springer US

Buch, Englisch, 175 Seiten, HC runder Rücken kaschiert, Format (B × H): 183 mm x 260 mm, Gewicht: 1330 g

presents a comprehensive description of power analysis and optimization techniques at the higher (architecture and behavior) levels of the design hierarchy, which are often the levels that yield the most power savings. This book describes power estimation and optimization techniques for use during high-level (behavioral synthesis), as well as for designs expressed at the register-transfer or architecture level.
surveys the state-of-the-art research on the following topics: power estimation/macromodeling techniques for architecture-level designs, high-level power management techniques, and high-level synthesis optimizations for low power.
will be very useful reading for students, researchers, designers, design methodology developers, and EDA tool developers who are interested in low-power VLSI design or high-level design methodologies.

Zielgruppe

Research

Autoren/Hrsg.

Raghunathan, Anand

Dey, Sujit

Jha, Niraj K.

Fachgebiete

• Geisteswissenschaften Design Produktdesign, Industriedesign
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise
• Mathematik | Informatik EDV | Informatik Professionelle Anwendung Computer-Aided Design (CAD)
• Technische Wissenschaften Technik Allgemein Computeranwendungen in der Technik
• Technische Wissenschaften Energietechnik | Elektrotechnik Elektrotechnik
• Technische Wissenschaften Technik Allgemein Konstruktionslehre und -technik
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
• Mathematik | Informatik EDV | Informatik Angewandte Informatik Computeranwendungen in Wissenschaft & Technologie

Inhaltsverzeichnis

1. Introduction.- 1.1 Low power design.- 1.2 Design abstraction and levels of the design hierarchy.- 1.3 Benefits of high-level power analysis and optimization.- 1.4 Book overview.- 2. Background.- 2.1 Sources of power consumption.- 2.2 Methods for reducing power and energy consumption.- 2.3 High-level design techniques.- 2.4 High-level synthesis application domains.- 3. Architecture-Level Power Estimation.- 3.1 Analytical power models.- 3.2 Characterization based activity and power macromodels.- 3.3 Power and switching activity estimation techniques for control logic.- 3.4 Conclusions.- 4. Power Management.- 4.1 Clock-based power management: Gated and multiple clocks.- 4.2 Pre-computation.- 4.3 Scheduling to enable power management.- 4.4 Operand isolation.- 4.5 Power management through constrained register sharing.- 4.6 Controller-based power management.- 4.7 Conclusions.- 5. High-Level Synthesis For Low Power.- 5.1 Behavioral transformations.- 5.2 Module selection.- 5.3 Resource sharing.- 5.4 Scheduling.- 5.5 Supply voltage vs. switched capacitance trade-offs.- 5.6 Optimizing memory power consumption during high-level synthesis.- 5.7 Reducing glitching power consumption during high-level design.- 5.8 Conclusions.- 6. Conclusions And Future Work.- References.