Pavlidis / Friedman Three-dimensional Integrated Circuit Design

1. Auflage 2010
ISBN: 978-0-08-092186-0
Verlag: Elsevier Science & Techn.
Format: EPUB
Kopierschutz: 6 - ePub Watermark

E-Book, Englisch, 336 Seiten

With vastly increased complexity and functionality in the 'nanometer era' (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. Connecting effectively (interconnect design) all of these chip elements has become the greatest determining factor in overall performance. 3-D integrated circuit design may offer the best solutions in the near future.
This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of 3-D integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of 3-D integrated circuits.
* Demonstrates how to overcome 'interconnect bottleneck' with 3-D integrated circuit design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers
* The FIRST book on 3-D integrated circuit design...provides up-to-date information that is otherwise difficult to find
* Focuses on design issues key to the product development cycle...good design plays a major role in exploiting the implementation flexibilities offered in the 3-D
* Provides broad coverage of 3-D integrated circuit design, including interconnect prediction models, thermal management techniques, and timing optimization...offers practical view of designing 3-D circuits

Vasilis F. Pavlidis received the B.S. and M.Eng. in electrical and computer engineering from the Democritus University of Thrace, Xanthi, Greece, in 2000 and 2002, respectively. He received the M.Sc. and Ph.D. degrees from, University of Rochester, Rochester, NY in 2003 and 2008, respectively. From 2000 to 2002, he was with INTRACOM S.A., Athens, Greece. In summer of 2007, he was with Synopsys Inc., Mountain View, California. His current research interests are in the area of interconnect modeling, 3-D integration, networks-on-chip, and related design issues in VLSI.

Autoren/Hrsg.

Pavlidis, Vasilis F.

Friedman, Eby G.

Inhaltsverzeichnis

1;Front Cover;1
2;Three-Dimensional Integrated Circuit Design;4
3;Copyright Page;5
4;Dedication Page;6
5;Contents;8
6;Preface;12
7;Acknowledgments;14
8;Chapter 1: Introduction;16
8.1;1.1. From the Integrated Circuit to the Computer;17
8.2;1.2. Interconnects, an Old Friend;20
8.3;1.3. Three-Dimensional or Vertical Integration;23
8.3.1;1.3.1. Opportunities for Three-Dimensional Integration;24
8.3.2;1.3.2. Challenges for Three-Dimensional Integration;26
8.4;1.4. Book Organization;28
9;Chapter 2: Manufacturing of 3-D Packaged Systems;32
9.1;2.1. Three-Dimensional Integration;32
9.1.1;2.1.1. System-in-Package;33
9.1.2;2.1.2. Three-Dimensional Integrated Circuits;33
9.2;2.2. System-on-Package;34
9.3;2.3. Technologies for System-in-Package;39
9.3.1;2.3.1. Wire-Bonded System-in-Package;39
9.3.2;2.3.2. Peripheral Vertical Interconnects;41
9.3.3;2.3.3. Area Array Vertical Interconnects;43
9.3.4;2.3.4. Metallizing the Walls of an SiP;45
9.4;2.4. Cost Issues for 3-D Integrated Systems;47
9.5;2.5. Summary;50
10;Chapter 3: 3-D Integrated Circuit Fabrication Technologies;52
10.1;3.1. Monolithic 3-D ICs;53
10.1.1;3.1.1. Stacked 3-D ICs;53
10.1.2;3.1.2. 3-D Fin-FETs;61
10.2;3.2. 3-D ICs with Through Silicon (TSV) or Interplane Vias;63
10.3;3.3. Contactless 3-D ICs;68
10.3.1;3.3.1. Capacitively Coupled 3-D ICs;68
10.3.2;3.3.2. Inductively Coupled 3-D ICs;70
10.4;3.4. Vertical Interconnects for 3-D ICs;71
10.4.1;3.4.1. Electrical Characteristics of Through Silicon Vias;76
10.5;3.5. Summary;78
11;Chapter 4: Interconnect Prediction Models;80
11.1;4.1. Interconnect Prediction Models for 2-D Circuits;81
11.2;4.2. Interconnect Prediction Models for 3-D ICs;84
11.3;4.3. Projections for 3-D ICs;88
11.4;4.4. Summary;92
12;Chapter 5: Physical Design Techniques for 3-D ICs;94
12.1;5.1. Floorplanning Techniques;94
12.1.1;5.1.1. Single-versus Multistep Floorplanning for 3-D ICs;96
12.1.2;5.1.2. Multi-Objective Floorplanning Techniques for 3-D ICs;99
12.2;5.2. Placement Techniques;102
12.2.1;5.2.1. Multi-Objective Placement for 3-D ICs;103
12.3;5.3. Routing Techniques;107
12.4;5.4. Layout Tools;110
12.5;5.5. Summary;112
13;Chapter 6: Thermal Management Techniques;114
13.1;6.1. Thermal Analysis of 3-D ICs;115
13.1.1;6.1.1. Closed-Form Temperature Expressions;116
13.1.2;6.1.2. Compact Thermal Models;123
13.1.3;6.1.3. Mesh-Based Thermal Models;125
13.2;6.2. Thermal Management Techniques without Thermal Vias;126
13.2.1;6.2.1. Thermal-Driven Floorplanning;126
13.2.2;6.2.2. Thermal-Driven Placement;132
13.3;6.3. Thermal Management Techniques Employing Thermal Vias;135
13.3.1;6.3.1. Region-Constrained Thermal Via Insertion;136
13.3.2;6.3.2. Thermal Via Planning Techniques;139
13.3.3;6.3.3. Thermal Wire Insertion;145
13.4;6.4. Summary;146
14;Chapter 7: Timing Optimization for Two-Terminal Interconnects;150
14.1;7.1. Interplane Interconnect Models;151
14.2;7.2. Two-Terminal Nets with a Single-Interplane Via;156
14.2.1;7.2.1. Elmore Delay Model of an Interplane Interconnect;156
14.2.2;7.2.2. Interplane Interconnect Delay;158
14.2.3;7.2.3. Optimum Via Location;160
14.2.4;7.2.4. Improvement in Interconnect Delay;163
14.3;7.3. Two-Terminal Interconnects with Multiple-Interplane Vias;166
14.3.1;7.3.1. Two-Terminal Via Placement Heuristic;170
14.3.2;7.3.2. Two-Terminal Via Placement Algorithm;174
14.3.3;7.3.3. Application of the Via Placement Technique;175
14.4;7.4. Summary;182
15;Chapter 8: Timing Optimization for Multiterminal Interconnects;184
15.1;8.1. Timing-Driven Via Placement for Interplane Interconnect Trees;184
15.2;8.2. Multiterminal Interconnect Via Placement Heuristics;188
15.2.1;8.2.1. Interconnect Trees;188
15.2.2;8.2.2. Single Critical Sink Interconnect Trees;189
15.3;8.3. Via Placement Algorithms for Interconnect Trees;191
15.3.1;8.3.1. Interconnect Tree Via Placement Algorithm (ITVPA);191
15.3.2;8.3.2. Single Critical Sink Interconnect Tree Via Placement Algorithm (SCSVPA);192
15.4;8.4. Via Placement Results and Discussion;192
15.5;8.5. Summary;198
16;Chapter 9: 3-D Circuit Architectures;200
16.1;9.1. Classification of Wire-Limited 3-D Circuits;201
16.2;9.2. Three-Dimensional Microprocessors and Memories;202
16.2.1;9.2.1. Three-Dimensional Microprocessor Logic Blocks;204
16.2.2;9.2.2. Three-Dimensional Design of Cache Memories;205
16.2.3;9.2.3. Architecting a 3-D Microprocessor - Memory System;210
16.3;9.3. Three-Dimensional Networks-on-Chip;212
16.3.1;9.3.1. 3-D NoC Topologies;213
16.3.2;9.3.2. Zero-Load Latency for 3-D NoC;215
16.3.3;9.3.3. Power Consumption in 3-D NoC;219
16.3.4;9.3.4. Performance and Power Analysis for 3-D NoC;221
16.3.5;9.3.5. Design Aids for 3-D NoCs;236
16.4;9.4. Three-Dimensional FPGAs;246
16.4.1;9.4.1. Design Aids for 3-D FPGAs;253
16.5;9.5. Summary;259
17;Chapter 10: Case Study: Clock Distribution Networks for 3-D ICs;262
17.1;10.1. MIT Lincoln Laboratories 3-D IC Fabrication Technology;263
17.2;10.2. 3-D Circuit Architecture;268
17.3;10.3. Clock Signal Distribution in 3-D Circuits;272
17.3.1;10.3.1. Timing Characteristics of Synchronous Circuits;273
17.3.2;10.3.2. Clock Distribution Network Structures within the Test Circuit;276
17.4;10.4. Experimental Results;280
17.5;10.5. Summary;287
18;Chapter 11: Conclusions;290
19;Appendix A: Enumeration of Gate Pairs in a 3-D IC;294
20;Appendix B: Formal Proof of Optimum Single Via Placement;296
21;Appendix C: Proof of the Two-terminal Via Placement Heuristic;298
22;Appendix D: Proof of Condition for Via Placement of Multiterminal Nets;302
23;References;304
24;Index;320