ASIC/SoC Functional Design Verification

A Comprehensive Guide to Technologies and Methodologies
Softcover Nachdruck of the original 1. Auflage 2018
ISBN: 978-3-319-86620-8
Verlag: Springer International Publishing

Buch, Englisch, 328 Seiten, Previously published in hardcover, Format (B × H): 155 mm x 235 mm, Gewicht: 546 g

This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon.  The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail.  He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, ReuseMethodology from Algorithm/ESL to RTL, and other overall methodologies.

Zielgruppe

Professional/practitioner

Autoren/Hrsg.

Mehta, Ashok B.

Fachgebiete

• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Schaltungsentwurf

Inhaltsverzeichnis

Chapter 1.Introduction.- Chapter 2.Functional Verification- Challeenges and Solution.- Chapter 3.SystemVerilog Paradigm.- Chapter 4. UVM.- Chapter 5.CRV.- Chapter 6.SVA.- Chapter 7.SFC.- Chapter 8.CDC.- Chapter 9.Low Power Verification.- Chapter 10. Static Verification.- Chapter 11.ESL.- Chapter 12. Hardware/Software Co-verification.- Chapter 13.- Analog Mixed Signals Verification.- Chapter 14.- SOC Interconnect Verification.- Chapter 15. The Complete Product Design Lifecycle.- Chapter 16. Voice Over IP.- Chapter 17. Cache Memory Subsystem Verification: UVM Agent Based.- Chapter 18. Cache Memory Subsystem Verification: ISS Based.

Über Autor(innen)

Ashok Mehta has been working in the ASIC/SoC design and verification field for over 20 years. He started his career at Digital Equipment Corporation (DEC) working as a CPU design engineer. He then worked at Data General, Intel (first Pentium Architecture Verification team) and after a route of couple of startups, worked at Applied Micro and currently at TSMC.

He was a very early adopter of Verilog and participated in Verilog, VHDL, iHDL (Intel HDL) and SDF (standard delay format) technical subcommittees. He has also been a proponent of ESL (Electronic System Level) designs. At TSMC he architected and went into production with two industry standard TSMC ESL Reference Flows that take designs from ESL to RTL while preserving the verification environment for reuse from ESL to RTL.

He holds 14 U.S. Patents in the field of SoC and 3DIC design verification.

He is also the author of Second Edition of the book “SystemVerilog Assertions and FunctionalCoverage – A comprehensive guide to languages, methodologies and applications”. Springer (June 2016).

Ashok earned an MSEE from University of Missouri.

In his spare time, he is an amateur photographer and likes to play drums on 70’s rock music driving his neighbors up the wall J