Nano Interconnects

Device Physics, Modeling and Simulation
1. Auflage 2024
ISBN: 978-0-367-61115-6
Verlag: CRC Press

Buch, Englisch, 238 Seiten, Format (B × H): 156 mm x 234 mm, Gewicht: 340 g

This textbook comprehensively covers on-chip interconnect dimension and application of carbon nanomaterials for modeling VLSI interconnect and buffer circuits.

It provides analysis of ultra-low power high speed nano-interconnects based on different facets such as material modeling, circuit modeling and the adoption of repeater insertion strategies and measurement techniques. It covers important topics including on-chip interconnects, interconnect modeling, electrical impedance modeling of on-chip interconnects, modeling of repeater buffer and variability analysis. Pedagogical features including solved problems and unsolved exercises are interspersed throughout the text for better understanding.

Aimed at senior undergraduate and graduate students in the field of electrical engineering, electronics and communications engineering for courses on Advanced VLSI Interconnects/Advanced VLSI Design/VLSI Interconnects/VLSI Design Automation and Techniques, this book:

- Provides comprehensive coverage of fundamental concepts related to nanotube transistors and interconnects.

- Discusses properties and performance of practical nanotube devices and related applications.

- Covers physical and electrical phenomena of carbon nanotubes, as well as applications enabled by this nanotechnology.

- Discusses the structure, properties, and characteristics of graphene-based on-chip interconnect.

- Examines interconnect power and interconnect delay issues arising due to downscaling of device size.

Zielgruppe

Postgraduate and Undergraduate Advanced

Autoren/Hrsg.

Khursheed, Afreen

Khare, Kavita

Fachgebiete

• Technische Wissenschaften Energietechnik | Elektrotechnik Elektrotechnik
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise

Inhaltsverzeichnis

Contents

List of Figures.ix

List of Tables.xiii

Preface.xvii

Acknowledgments.xix

About the Authors.xxi

Chapter 1 Prefatory Concepts and More.1

Chapter 2 Interconnect Modeling.21

Chapter 3 Repeater Buffer Modeling.103

Chapter 4 Signal Integrity Analysis.175

Index.213

Über Autor(innen)

Dr Afreen Khursheed is working as Assistant professor in IIIT Bhopal. She has received B.E (EC) with honours in 2005 & M.Tech with honours in 2009 in VLSI and EMBEDDED SYSTEM from M.A.N.I.T, Bhopal. She earned her Doctorate in Nanotechnology from M.A.N.I.T, Bhopal. She has got 13 years of teaching and research experience, and has successfully guided M.Tech thesis. To her credit, Dr Afreen has publications in various international conferences and SCI (Q1/Q2) indexed journals, and is co author of two books on Low Power VLSI Design. Dr Afreen has also reviewed manuscripts for international journals and also served as the editorial board member of UGC journals and conferences. She has presented Poster and also delivered lectures in various national and international events and conferences held at M.A.N.I.T, Texas A and M University, Qatar university etc. Her area of interest includes high speed nanoelectronic circuit modelling for portable devices. Ultra low power subthreshold circuit simulation and device modelling using CNT and GNR. Her current area of interdisciplinary research focuses on VLSI implementation on a real-time operating system using spintronics.

Dr. Kavita Khare received her B.Tech degree in Electronics and Communication Engineering in 1989, M.Tech. degree in Digital Communication Systems in 1993 and Ph.D. degree in the field of VLSI Design in 2004. She has got nearly 25 years teaching experience. She has 190 publications in various international conferences and journals like IEEE, springer, Elsivier, Oxford press, Hindawi, European Transactions on Telecommunications, Inderscience publications., Taylor and Fancis, CSIR (NISCAIR), AMSE. She has guided nearly 14 PhD thesis and nearly 34 Mtech thesis. She got best paper award at International Conference at France. She is Coordinator of Short term Courses on VLSI Design organized at MANIT Bhopal. She is Reviewer of Papers of IEEE Jour. Of Circuits & Systems, Microelectronics Journal, Elsevier, International Journal AMSE (France), Institute of Engineers and many International Conferences. She is Editor/ Chief Advisory Board Member of some International Journals. Currently, she is working as Professor and Head Dept of Electronics and Communication Engineering in MANIT, Bhopal, INDIA. Her fields of interest are VLSI design and Communication Systems. Her research mainly includes design of arithmetic circuits and various communication algorithms related to synchronization, estimation and routing. She is a Fellow IETE (India) and member of IEEE, Life Member ISTE.