E-Book, Englisch, 162 Seiten
From RF to mmW
E-Book, Englisch, 162 Seiten
ISBN: 978-0-12-418681-1
Verlag: Elsevier Science & Techn.
Format: EPUB
Kopierschutz: 6 - ePub Watermark
Autoren/Hrsg.
Weitere Infos & Material
1;Front Cover;1
2;Linearization and Efficiency Enhancement Techniques for Silicon Power Amplifiers;4
3;Copyright Page;5
4;Contents;6
5;List of Contributors;8
6;1 Holistic Approaches for Power Generation, Linearization, and Radiation in CMOS;10
6.1;1.1 Self-Healing Integrated Circuits;15
6.1.1;1.1.1 Self-Healing mm-Wave Power Amplifier;18
6.1.2;1.1.2 Sensing RF Power;19
6.1.3;1.1.3 Sensing DC Current;19
6.1.4;1.1.4 Actuating Quiescent Operating Point;22
6.1.5;1.1.5 Data Conversion and Healing Algorithm;23
6.1.6;1.1.6 Measurement Results;24
6.2;1.2 Segmented Power Mixer for mm-Wave Transmitters;29
6.2.1;1.2.1 Key Building Blocks;31
6.2.2;1.2.2 Measurement Results;33
6.3;1.3 Distributed Active Radiation;37
6.3.1;1.3.1 DAR Design Approach;37
6.3.2;1.3.2 Architecture;39
6.3.3;1.3.3 Measurement Results;40
6.4;References;42
7;2 Cartesian Feedback with Digital Enhancement for CMOS RF Transmitter;44
7.1;2.1 Introduction;44
7.2;2.2 CFB Loop;45
7.3;2.3 CFB Digital Part Implementation;49
7.3.1;2.3.1 Phase Estimation;50
7.3.1.1;2.3.1.1 “atan”-Based Architecture;50
7.3.1.1.1;2.3.1.1.1 LUT-Based Architecture;51
7.3.1.1.2;2.3.1.1.2 CORDIC-Based Architecture;51
7.3.1.2;2.3.1.2 “Modulo” Function Implementation;53
7.3.2;2.3.2 Vector Rotation;53
7.3.2.1;2.3.2.1 LUT and Multipliers Solution;53
7.3.2.2;2.3.2.2 CORDIC-Based Solution;53
7.3.3;2.3.3 Subtraction;53
7.3.4;2.3.4 Improvement of CFB CORDIC-Based Architecture;54
7.3.4.1;2.3.4.1 Modification of the CFB Algorithm;54
7.3.4.2;2.3.4.2 New Architecture;54
7.4;2.4 Analog Part Implementation;56
7.5;2.5 Linearized Transmitter Results;58
7.6;2.6 Power Consumption and Size Considerations;59
7.7;2.7 Conclusion;61
7.8;References;61
8;3 Transmitter Linearity and Energy Efficiency;64
8.1;3.1 Introduction;64
8.2;3.2 The PA Design Problem;64
8.3;3.3 A Reverse Design Approach;70
8.3.1;3.3.1 PA Operating Modes;72
8.3.2;3.3.2 What Does “Gain” Mean When Nonlinear?;74
8.3.3;3.3.3 Apparent Linearity: Output Signal Accuracy;76
8.3.4;3.3.4 Stage Series Resistance;78
8.4;3.4 Output Power Control;79
8.5;3.5 OBO Elimination;81
8.6;3.6 Stabilities: Circuit, Thermal, and Manufacturing;82
8.6.1;3.6.1 Stability of the Circuit;82
8.6.2;3.6.2 Stability Over Temperature;83
8.6.3;3.6.3 Stability Across Manufacturing;84
8.7;3.7 Aging;85
8.8;3.8 Categorizing C-mode Operation;86
8.9;3.9 Conclusion;87
8.10;References;89
9;4 mmW Doherty;92
9.1;4.1 Introduction;92
9.2;4.2 Doherty Amplifier;93
9.2.1;4.2.1 Doherty Structure;93
9.2.2;4.2.2 Nonidealities in Doherty Structure;96
9.3;4.3 mmW Doherty Amplifiers;98
9.3.1;4.3.1 Silicon Transistors in mmW Doherty Structure;99
9.3.2;4.3.2 Passive Components in mmW Doherty Structure;103
9.3.3;4.3.3 Other Techniques;111
9.4;References;113
10;5 Reliable Power Amplifier;116
10.1;5.1 Introduction;116
10.2;5.2 Effect of CMOS Technology Scaling on Thermal Management;116
10.3;5.3 Metal Interconnects Electromigration;120
10.4;5.4 Time-Dependent Dielectric Breakdown (TDDB);121
10.5;5.5 Hot Carrier Injection;123
10.5.1;5.5.1 DC Model;124
10.5.2;5.5.2 RF Model;125
10.6;5.6 Electrostatic Static Discharge;127
10.6.1;5.6.1 Human Body Model;127
10.6.2;5.6.2 Machine Model;128
10.6.3;5.6.3 Charged Device Model;128
10.6.4;5.6.4 ESD Protection;129
10.7;5.7 Voltage Standing Wave Ratio;130
10.8;5.8 Power Amplifier Design for Reliability;134
10.8.1;5.8.1 Mission Profile Analysis;134
10.9;5.9 Intrinsically Robust Design;136
10.10;5.10 Self-Healing Design;139
10.11;5.11 Conclusion;140
10.12;References;141
11;6 Efficiency Enhancement for THz Power Amplifier;144
11.1;6.1 Introduction;144
11.2;6.2 Power Amplifier Performance Trade-offs Toward THz Operation;147
11.2.1;6.2.1 Output Power Limitations in Silicon Process Technologies;148
11.2.2;6.2.2 Power Gain Trade-offs;151
11.2.3;6.2.3 PAE Trade-offs;152
11.2.4;6.2.4 Impedance Match for Maximum Power Delivery;153
11.2.4.1;6.2.4.1 Load-Line Match Versus Conjugate-Matching;154
11.2.4.2;6.2.4.2 Sizing of Tuning Elements;155
11.3;6.3 Device Scaling Considerations for Future High-Power THz Applications;155
11.3.1;6.3.1 Calculation of Output Resistance in Terms of the Device Parasitics;157
11.4;6.4 Summary/Table;160
11.5;References;160
Chapter 1 Holistic Approaches for Power Generation, Linearization, and Radiation in CMOS
Ali Hajimiri and Kaushik Dasgupta, California Institute of Technology (Caltech), Pasadena, CA The field of wireless communications has experienced an exponential growth over the past four decades, going from the realm of science fiction to becoming so ubiquitous and natural that the younger generations have a difficult time imagining a world without it. This has been made possible through many breakthroughs in our understanding of the nature of wireless communications and, more importantly, numerous innovative enabling technologies that have made personal wireless communication an everyday reality. Keywords
Wireless; communications; technologies The field of wireless communications has experienced an exponential growth over the past four decades, going from the realm of science fiction to becoming so ubiquitous and natural that the younger generations have a difficult time imagining a world without it. This has been made possible through many breakthroughs in our understanding of the nature of wireless communications and, more importantly, numerous innovative enabling technologies that have made personal wireless communication an everyday reality. Creating the fascinating edifice that is the connected world of ubiquitous access to information has been made possible through effective complexity management performed through a process of divide and conquer. This is possible through a systematic process of specialization and subspecialization in electrical engineering and its associated fields that have been part of the historic trends in this area, creating levels of abstractions within which a small group of people can design for a given set of specifications. This is what has enabled this complexity management. These levels of abstraction have played a key role in our ability to deploy such complex systems such as our wireless communication systems. A typical example of the hierarchy of these levels of abstractions is shown in Figure 1.1.
Figure 1.1 Levels of abstraction in a system. In radiofrequency integrated circuit (RFIC) design, the same trends have been present since the inception of RFIC and monolithic microwave integrated circuits (MMICs). The system architectures are defined and created at a separate time and by a different group of engineers than those who define the chip architectures and those who design the transistor levels circuit blocks. The electromagnetic design (e.g., antenna and off-chip passive components) has also been generally performed by yet another group of designers. This partitioning of tasks has enabled speedy and tractable design of such systems; however, it has also created impediments in the way of innovation by limiting the number of possibilities that can be considered in the design of the entire system by constraining the design space to a limited subset of all possibilities (Figure 1.2).
Figure 1.2 The design space and its subspaces, limiting the range of design possibilities considered. These somewhat arbitrary levels of abstractions have resulted in some of the classical approaches to RFIC design, with the individual circuit elements considered as lumped components and the effects of nonidealities and the couplings modeled using additional parasitic components. This allows for continuous application of long-known circuit simulation techniques essentially based on nodal analysis (Figure 1.3). Even in the realm of MMIC, the approach has been only partially extended by analyzing the nonlumped blocks such as transmission lines and on-chip antennas as separate units and representing them as scatter parameter boxes (Figure 1.4).
Figure 1.3 A classical RFIC integrated circuit.
Figure 1.4 A standard MMIC operating at high frequencies. However, the ever-increasing complexity of wireless systems and the associated integrated circuits combined with the constantly growing standards and frequency bands of operations have created strong interconnections among these levels of abstractions. This is a challenge if examined from the point of view of classical levels of abstractions. It manifests itself as a cohort of problems such as cross talk, electromagnetic coupling, impedance mismatches, parasitic elements, and others. This situation has been exacerbated by the scaling of the transistors; the cutoff wavelength (the wavelength associated with the cutoff frequency of the transistors) is constantly shrinking and the dimensions of the integrated circuits have been growing, as conceptually shown in Figure 1.5. This has resulted in a crossing of the two curves (which happens approximately at the 250-nm CMOS nodes), leaving us in a nonlumped regime.
Figure 1.5 The conceptual plot of the cutoff wavelengths and chip dimensions versus time. However, if one is willing to look at the problem in a broader context and not be confined by the classical levels of abstraction, then this can present a tremendous opportunity to overcome some of the classical problems in RFIC design. This can be accomplished by using a holistic approach to co-design of various parts of the system [1,2]. The holistic approach relies on a more close interaction of the electromagnetics and the transistors. It generally achieves this through a large number of transistors and small passive structures with strong electromagnetic coupling operating in concert (Figure 1.6).
Figure 1.6 Highly parallel, strongly coupled holistic integrated EM structures. These structures can be used to enable simultaneous and active control of the electric and magnetic field profiles (E and H), enabling a much richer combination of field profiles and a much broader set of functions. This is an example of holistic integration of architecture, circuits, electromagnetics, and devices. Although promising, such holistic approaches require the designers to obtain a broader set of skills ranging from a more thorough understanding of the system level matters to deeper device and physics-oriented aspects of the system. However, once the walls between classical levels of abstraction are removed, it becomes possible to design circuits that can outperform the classical solutions. More sophisticated approaches to simulation of these systems, which necessitate rethinking of the whole design flow, are also necessary. A holistic approach inevitably leads to several underlying trends in the design methodology. Some of those trends are: 1. Parallelism: One of the most significant features of today’s silicon integrated circuits is the practically unlimited number of transistors they offer. As integrated circuits find their way into every conceivable part of wireless systems, it becomes essential to take full advantage of the large number of transistors. This unlimited number of transistors, however, comes at the cost of more limited power-handling capability of individual ones. This makes electromagnetically parallel structures much more compelling and a necessity in these approaches. This mindset can be loosely stated as “the army of mice versus the giant elephant.” 2. Concurrency: While related to parallelism at some level, concurrency in this context refers to various signal paths that process potentially different pieces of information in parallel. 3. Highly reconfigurable, modifiable, and healable: To be able to address various applications and take full advantage of the co-integration at various levels of abstraction, highly reconfigurable and dynamically modifiable systems are essential. In the presence of a large number of elements involved, this reconfigurability must be enhanced and automated, giving rise to so-called self-healing systems. Such self-healing systems are highly conducive to holistic approaches. We discuss these themes through a few examples in the remainder of this chapter. 1.1 Self-Healing Integrated Circuits
The past few decades have witnessed aggressive CMOS scaling, primarily driven by the demand for cost-, area-, and power-efficient processors for desktops as well as mobile chipsets. The number of transistors per chip has increased from a few thousand in the 1980s to a few billion in the latest desktop processors. More recently, pure dimensional scaling has become less effective and other performance enhancement techniques like strained Si [3,4], tri-gate [5] FinFETs, and others have been widely adopted by the semiconductor industry. While bringing significant improvements in power consumption, area, and overall performance, such scaling also comes at the cost of increased variations—both between chips and on the same chip. We can broadly categorize these variations into static variations and dynamic variations. Static variations can mostly be attributed to the fabrication process itself and is dominated by two major effects—random dopant fluctuations (RDFs) and line edge roughness (LER). As shown in Figure 1.7A, the average number of dopant atoms in the channel region has scaled down dramatically, from a few hundred in 130-nm CMOS to less than one hundred in modern CMOS transistors. Any variation in both the number and the actual placement of these dopants (RDF) thereby leads to significant changes in the transistor performance. LER is caused by imperfections during the...
