Golshan The Art of Timing Closure

Advanced ASIC Design Implementation
1. Auflage 2020
ISBN: 978-3-030-49636-4
Verlag: Springer International Publishing
Format: PDF
Kopierschutz: 1 - PDF Watermark

E-Book, Englisch, 204 Seiten, eBook

The Art of Timing Closure is written using a hands-on approach to describe advanced concepts and techniques using Multi-Mode Multi-Corner (MMMC) for an advanced ASIC design implementation. It focuses on the physical design, Static Timing Analysis (STA), formal and physical verification.
The scripts in this book are based on Cadence® Encounter System™. However, if the reader uses a different EDA tool, that tool’s commands are similar to those shown in this book.

The topics covered are as follows:
Data StructuresMulti-Mode Multi-Corner AnalysisDesign ConstraintsFloorplan and Timing Placement and TimingClock Tree SynthesisFinal Route and TimingDesign Signoff
Rather than go into great technical depth, the author emphasizes short, clear descriptions which are implemented by references to authoritative manuscripts. It is the goal of this book to capture the essenceof physical design and timing analysis at each stage of the physical design, and to show the reader that physical design and timing analysis engineering should be viewed as a single area of expertise.
This book is intended for anyone who is involved in ASIC design implementation -- starting from physical design to final design signoff. Target audiences for this book are practicing ASIC design implementation engineers and students undertaking advanced courses in ASIC design.

Zielgruppe

Professional/practitioner

Autoren/Hrsg.

Golshan, Khosrow

Inhaltsverzeichnis

Chapter 1. Introduction.- Chapter 2. Design Implementation Data Structures and Settings.- Chapter 3. Design Constraints Development.- Chapter 4. Multiple Modes and Multiple Corners Development.- Chapter 5. Concurrent Floor Planning and Placement.- Chapter 6. Placement and Timing Analysis.- Chapter 7. Clock Tree Synthesis and Timing Analysis.- Chapter 8. Detail Route and Timing, Power Analysis.- Chapter 9. Final Route and Timing Closure in all Modes and Corners.- Chapter 10. Functional and Physical Verification.

Über Autor(innen)

Khosrow Golshan was Division Director at Conexant System Inc. and Technical Director at Synaptics Inc. while managing and directing worldwide ASIC design implementation and standard cell and I/O library development for various silicon process nodes. Prior to that he was Group Technical Staff at Texas Instrument’s R&D and Process Development Laboratory  responsible for processing silicon test-chip design and digital/mixed-signal ASIC development. He has over twenty years’ experience in ASIC design implementation methodology, flow development, and digital ASIC libraries design.
He is the author of
Physical Design Essentials—An ASIC Design Implementation Perspective
. In addition, he has published many technical articles and has held several US patents.
The author has earned advanced degrees in the areas of Electrical Engineering(West Coast University, Los Angeles, CA. Engineering Dept.), Applied Mathematics(Southern Methodist University, Dallas, TX. MathematicsDept.) and a Bachelor of Science in Electronic Engineering(DeVry University, Dallas, TX. Engineering Dept.). He is also an IEEE life member.