A Roadmap for Formal Property Verification

2006. Auflage 2006
ISBN: 978-1-4020-4757-2
Verlag: Springer

Buch, Englisch, 252 Seiten, Format (B × H): 162 mm x 247 mm, Gewicht: 1220 g

Integrating formal property verification (FPV) into an existing design process raises several interesting questions. Have I written enough properties? Have I written a consistent set of properties? What should I do when the FPV tool runs into capacity issues? This book develops the answers to these questions and fits them into a roadmap for formal property verification – a roadmap that shows how to glue FPV technology into the traditional validation flow. A Roadmap for Formal Property Verification explores the key issues in this powerful technology through simple examples – you do not need any background on formal methods to read most parts of this book.

Zielgruppe

Research

Autoren/Hrsg.

Dasgupta, Pallab

Fachgebiete

• Mathematik | Informatik EDV | Informatik Informatik Logik, formale Sprachen, Automaten
• Mathematik | Informatik EDV | Informatik Professionelle Anwendung Computer-Aided Design (CAD)
• Technische Wissenschaften Technik Allgemein Konstruktionslehre und -technik
• Mathematik | Informatik EDV | Informatik Technische Informatik Hochleistungsrechnen, Supercomputer
• Mathematik | Informatik EDV | Informatik Angewandte Informatik Computeranwendungen in Wissenschaft & Technologie
• Technische Wissenschaften Technik Allgemein Computeranwendungen in der Technik
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Mikroprozessoren
• Technische Wissenschaften Technik Allgemein Technik: Allgemeines
• Geisteswissenschaften Design Produktdesign, Industriedesign
• Technische Wissenschaften Elektronik | Nachrichtentechnik Elektronik Bauelemente, Schaltkreise

Inhaltsverzeichnis

Languages for Temporal Properties.- How Does the Property Checker Work?.- Is My Specification Consistent?.- Have I Written Enough Properties?.- Design Intent Coverage.- Test Generation Games.- A Roadmap for Formal Property Verification.

Über Autor(innen)

The author leads the Formal Verification Group at the Indian Institute of Technology, Kharagpur (http://www.facweb.iitkgp.ernet.in/~pallab/forverif.html). He has collaborations with leading companies, including Intel, Sun Microsystems, Synopsys, Texas Instruments, National Semiconductors, General Motors, Interra Systems and Virtio Corp, on developing formal methods for design verification. The author is a senior member of IEEE.